Altera Avalon Verification IP Suite User Manual download pdf (Page 84)

set_enable_a_register_incoming_signals()

set_enable_a_register_incoming_signals()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion that ensures waitrequest is asserted at all times and

deasserts a single clock cycle after a read or write transaction.

Description:

Verilog HDLLanguage support:

set_enable_a_waitrequest_during_reset()

set_enable_a_waitrequest_during_resetl()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion that ensures that waitrequest is asserted if reset is

asserted. Disabled when waitrequest is not supported.

Description:

Verilog HDLLanguage support:

set_enable_a_waitrequest_timeout()

set_enable_a_waitrequest_timeout()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion that ensures waitrequest is not asserted continuously

for more than maximum allowed timeout period. Disabled when either

waitrequest is not supported or the maximum timeout period is less than

Description:

Verilog HDLLanguage support:

Avalon-MM Monitor

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set_enable_a_register_incoming_signals()

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Altera Avalon Verification IP Suite User Manual Page 84