Altera Avalon Verification IP Suite User Manual download pdf (Page 175)

100

101

signal_api_call

signal_api_callPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Triggers when a client make an API call.Description:

Verilog HDLLanguage support:

write()

write()Prototype:

VHDL:

bit[CDT_ADDRESS_W-1:0] address

logic[DATA_W-1:0] data

bfm_id

req_if(bfm_id)

Verilog HDL:

bit[CDT_ADDRESS_W-1:0] address

logic[DATA_W-1:0] data

Arguments:

voidReturns:

Overwrites the memory content at an address you specify.Description:

Verilog HDL, VHDLLanguage support:

External Memory BFM

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