Altera Avalon Verification IP Suite User Manual download pdf (Page 201)

set_result_delay()

void set_result_delay()Prototype:

Verilog HDL: ci_data_t delay

VHDL: ci_data_t delay, bfm_id, req_if(bfm_id)

Arguments:

voidReturns:

Sets the instruction result delay.Description:

Verilog HDL, VHDLLanguage support:

set_result_err_inject()

void set_result_err_inject()Prototype:

Verilog HDL: int err_inj

VHDL: int err_inj, bfm_id, req_if

Arguments:

voidReturns:

Sets the instruction result to execute in pre-defined error.Description:

Verilog HDL, VHDLLanguage support:

set_result_value()

void set_result_value()Prototype:

Verilog HDL: ci_data_t value

VHDL: ci_data_t value, bfm_id, req_if(bfm_id)

Arguments:

voidReturns:

Sets the instruction result.Description:

Verilog HDL, VHDLLanguage support:

signal_fatal_error

signal_fatal_errorPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that a fatal error has occured in this module.Description:

Verilog HDLLanguage support:

Altera Corporation

Nios II Custom Instruction Slave BFM

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set_result_delay()

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Altera Avalon Verification IP Suite User Manual Page 201