Altera Avalon Verification IP Suite User Manual download pdf (Page 203)

signal_result_driven

signal_result_drivenPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that a result has been driven from the slave interface.Description:

Verilog HDLLanguage support:

signal_unknown_instruction_received

signal_unknown_instruction_receivedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that a change has occured on the instruction interface and there is an

unknown value.

Description:

Verilog HDLLanguage support:

Altera Corporation

Nios II Custom Instruction Slave BFM

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