Altera Avalon Verification IP Suite User Manual download pdf (Page 64)

get_pending_write_latency_cycle()

int get__cycle()Prototype:

Verilog HDL: None

VHDL: pending_write_latency, bfm_id, req_if(bfm_id)

Arguments:

intReturns:

Queries the write command queue to determine the cycles needed for the Slave

BFM to complete the current write response.

Description:

Verilog HDL, VHDLLanguage support:

get_response_queue_size()

int get_response_queue_size()Prototype:

Verilog HDL: None

VHDL: response_queue_size, bfm_id, req_if(bfm_id)

Arguments:

intReturns:

Queries the response queue to determine number of response descriptors pending.Description:

Verilog HDL, VHDLLanguage support:

vget_slave_bfm_status

bit get_slave_bfm_statusPrototype:

Verilog HDL: None

VHDL: slave_bfm_status, bfm_id, req_if(bfm_id)

Arguments:

bitReturns:

Queries the Slave BFM component to determine when the read transaction in the

Slave BFM has reached the maximum read transactions. A return value of 1 means

that the Slave BFM can no longer accept a new read command.

Description:

Verilog HDL, VHDLLanguage support:

Avalon-MM Slave BFM

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get_pending_write_latency_cycle()

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Altera Avalon Verification IP Suite User Manual Page 64