Altera Avalon Verification IP Suite User Manual Page 112

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signal_write_response_complete
signal_write_response_completePrototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
voidReturns:
Notifies the testbench that the write response has been received and inserted
into the response queue.
Description:
Verilog HDLLanguage support:
Avalon-MM Monitor
Altera Corporation
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signal_write_response_complete
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