Altera Avalon Verification IP Suite User Manual download pdf (Page 190)

signal_max_result_queue_size

signal_max_result_queue_sizePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the maximum pending result queue size threshold has been exceeded.Description:

Verilog HDLLanguage support:

signal_min_instruction_queue_size

signal_min_instruction_queue_sizePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the pending instruction queue size is below the minimum threshold.Description:

Verilog HDLLanguage support:

signal_min_result_queue_size

signal_min_result_queue_sizePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the pending result queue size is below the minimum threshold.Description:

Verilog HDLLanguage support:

signal_result_received

signal_result_receivedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that a result has been received.Description:

Verilog HDLLanguage support:

Altera Corporation

Nios II Custom Instruction Master BFM

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signal_max_result_queue_size

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Altera Avalon Verification IP Suite User Manual Page 190