Altera Avalon Verification IP Suite User Manual download pdf (Page 168)

signal_grant_deasserted_while_request_remain_asserted

signal_grant_deasserted_while_request_remain_assertedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

None.Arguments:

voidReturns:

Triggers when the grant signal changes value from high to low while the request

signal remains asserted.

Description:

Verilog HDLLanguage support:

signal_interface_granted

signal_interface_grantedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

None.Arguments:

voidReturns:

Triggers when the grant signal is asserted.Description:

Verilog HDLLanguage support:

signal_max_transaction_queue_size

signal_max_transaction_queue_sizePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

None.Arguments:

voidReturns:

Triggers when the size of the pending queue exceeds the maximum size.Description:

Verilog HDLLanguage support:

Altera Corporation

Tri-State Conduit BFM

Send Feedback

12-9

signal_grant_deasserted_while_request_remain_asserted

1 2 ... 163 164 165 166 167 168 169 170 171 172 173 ... 223 224

Comments to this Manuals

No comments