Altera Avalon Verification IP Suite User Manual download pdf (Page 189)

signal_fatal_error

signal_fatal_errorPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that a fatal error has occured in this module.Description:

Verilog HDLLanguage support:

signal_instructions_completed

signal_instructions_completedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that all instructions in the BFM has been executed.Description:

Verilog HDLLanguage support:

signal_instruction_start

signal_instruction_startPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that an instruction has been driven to the interface.Description:

Verilog HDLLanguage support:

signal_max_instruction_queue_size

signal_max_instruction_queue_sizePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the maximum pending instruction queue size threshold has been

exceeded.

Description:

Verilog HDLLanguage support:

Nios II Custom Instruction Master BFM

Altera Corporation

Send Feedback

signal_fatal_error

14-14

1 2 ... 184 185 186 187 188 189 190 191 192 193 194 ... 223 224

No comments

Altera Avalon Verification IP Suite User Manual Page 189