Altera Avalon Verification IP Suite User Manual download pdf (Page 81)

set_enable_a_half_cycle_reset_legal()

set_enable_a_half_cycle_reset_legal()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion that ensures reset is asserted correctly.Description:

Verilog HDLLanguage support:

set_enable_a_less_than_burstcount_max_size()

set_enable_a_less_than_burstcount_max_size()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion that ensures burstcount size is less than or equal to

the maximum burst size, 2**(AV_BURSTCOUNT_W-1).Disabled when either

burst transfers are not supported or the bust size is less than 1.

Description:

Verilog HDLLanguage support:

set_enable_a_less_than_maximumpendingreadtransactions()

set_enable_a_less_than_maximumpendingreadtransactions()Prototype:

Verilog HDL: Boolean

VHDL: N.A.

Arguments:

voidReturns:

Enables an assertion that ensures that the number of pending read transfers

is less than maximumPendingReadTransactions. Disabled when either read

is not supported or maximumPendingReadTransactions is less than 1.

Description:

Verilog HDLLanguage support:

Altera Corporation

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Altera Avalon Verification IP Suite User Manual Page 81