Altera JESD204B IP User Manual download pdf (Page 84)

6. You can enable internal serial loopback by setting the rx_seriallpbken input signal. You can

dynamically toggle this input signal. When toggled to 1, the RX path takes the serial input from the TX

path internally in the FPGA. When toggled to 0, the RX path takes the serial input from the external

converter device. During internal serial loopback mode, the assembler takes input from the pattern

generator.

7. A single serial port interface (SPI) master instance can control multiple SPI slaves. The SPI master is a

4-wire instance. If the SPI slave is a 3-wire instance, use a bidirectional I/O buffer in between the

master and slave to interface the 4-wire master to 3-wire slave.

8. The SPI protocol interface. All slaves share the same data lines (MISO and MOSI, or DATAIO). Each

slave has its own slave select or chip select line (SS_n).

9. The PLL takes the device clock from an external clock chip as the input reference. The PLL generates

two output clocks (utilizing two output counters from a single VCO). Clock 1 is the frame clock for the

transport layer, pattern generator, and pattern checker. Clock 2 is the link clock for the transport and

link layer.

10.The control unit implements a memory initialization file (MIF) method for configuring the SPI. Each

MIF corresponds to a separate external converter per device or clock chip. For example, in a system

that interacts with both DAC and ADC, two MIFs are needed—one each for DAC and ADC.

11.The PLL reconfiguration and transceiver reconfiguration controller instances are only required for run

time reconfiguration of the data rate.

Design Example Components

The design example for the JESD204B IP core consists of the following components:

• PLL

• PLL reconfiguration

• Transceiver reconfiguration controller

• Transceiver reset controller

• Pattern generator

• Pattern checker

• Assembler and deassembler (in the transport layer)

• SPI

• Control unit

The following sections describe in detail the function of each component.

PLL

The design example requires four different clock domains—device clock, management clock, frame clock,

and link clock.

Typically, the device clock is generated from an external converter or a clock device while the

management clock (AVS clock) is generated from an on-board 100 MHz oscillator.

For instance, if the JESD204B IP core is configured at data rate of 6.144 Gbps, transceiver reference clock

frequency of 153.6 MHz, and number of octets per frame (F) = 2, the example below indicates the PLL

clock frequencies:

• device clock = transceiver reference clock frequency = 153.6 MHz

• link clock = 6144 / 40 = 153.6 MHz

• frame clock = 153.6 x 32 / (8 x 2) = 307.2 MHz

UG-01142

2015.05.04

Design Example Components

5-3

JESD204B IP Core Design Guidelines

Altera Corporation

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