Altera JESD204B IP User Manual Page 2
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Contents
JESD204B IP Core Quick Reference...................................................................1-1
About the JESD204B IP Core..............................................................................2-1
Datapath Modes...........................................................................................................................................2-3
IP Core Variation.........................................................................................................................................2-3
JESD204B IP Core Configuration..............................................................................................................2-4
Run-Time Configuration................................................................................................................2-4
Channel Bonding......................................................................................................................................... 2-5
Performance and Resource Utilization.....................................................................................................2-6
Getting Started.................................................................................................... 3-1
Introduction to Altera IP Cores.................................................................................................................3-1
Installing and Licensing IP Cores..............................................................................................................3-2
Upgrading IP Cores.....................................................................................................................................3-2
IP Catalog and Parameter Editor...............................................................................................................3-5
Design Walkthrough................................................................................................................................... 3-6
Creating a New Quartus II Project................................................................................................3-6
Parameterizing and Generating the IP Core................................................................................3-7
Generating and Simulating the IP Core Testbench.................................................................... 3-8
Compiling the JESD204B IP Core Design..................................................................................3-10
Programming an FPGA Device................................................................................................... 3-11
JESD204B IP Core Design Considerations............................................................................................ 3-11
Integrating the JESD204B IP core in Qsys................................................................................. 3-11
Pin Assignments.............................................................................................................................3-12
Adding External Transceiver PLL............................................................................................... 3-13
Timing Constraints For Input Clocks.........................................................................................3-13
JESD204B IP Core Parameters.................................................................................................................3-16
JESD204B IP Core Component Files......................................................................................................3-21
JESD204B IP Core Testbench.................................................................................................................. 3-21
Testbench Simulation Flow..........................................................................................................3-23
JESD204B IP Core Functional Description........................................................4-1
Transmitter...................................................................................................................................................4-4
TX Data Link Layer..........................................................................................................................4-5
TX PHY Layer.................................................................................................................................. 4-8
Receiver......................................................................................................................................................... 4-8
RX Data Link Layer..........................................................................................................................4-9
RX PHY Layer................................................................................................................................ 4-12
Operation....................................................................................................................................................4-13
Operating Modes........................................................................................................................... 4-13
TOC-2
JESD204B IP Core User Guide
Altera Corporation
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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