Altera JESD204B IP User Manual Page 120
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Figure 5-16: Example of MIF Format and Content
-- MIF content for ADC
WIDTH=24; -- the size of data in bits
DEPTH=8; -- the size of memory in words
ADDRESS_RADIX=UNS; -- the radix for address values
DATA_RADIX=BIN; -- the radix for data values
CONTENT BEGIN
0 : 000000000101111100010101; -- write 0x15 to link control 1 register 0x5F to disable the lane
1 : 000000000101111001000100; -- write 0x44 to quick config register 0x5E for L=4, M=4
2 : 000000000110010011000000; -- write 0xC0 to DID register 0x64
3 : 000000000110111000000011; -- write 0x03 to parameter SCR/L register 0x6E to disable scrambler
4 : 000000000111000000001111; -- write 0x0F to parameter K register 0x70 for K=16 in base IP core
5 : 000000000000110100000100; -- write 0x04 to test mode register 0x0D for checkerboard test pattern
6 : 000000000101111100010100; -- write 0x14 to link control 1 register 0x5F to enable the lane
7 : 111111111111111111111111; -- indicates end of mif or end of programming sequence
END;
The initial values for each address and sequence is defined based on the requirement of the external
converter and clock devices. The example above is based on 24-bit SPI write-only programming.
The last word must not be a valid data and must be set to all 1's to indicate the end of the MIF or
programming sequence. This is because each converter device may have a different number of
programmable registers and hence involves a different number of MIF words. In this design example,
three ROMs are used by default for each external ADC, DAC, and clock devices. If either one of the device
is not used, a single word MIF with all 1's can be created.
Note:
The MIFs in this design example is an example for a particular converter device. You must define
the MIF content based on the requirement of the external converter devices.
Finite State Machine (FSM)
The steps below describe the FSM flow:
1. Initialize the SPI:
a. Perform a read transaction from the ROM on per word basis and write to the SPI master for SPI
write transaction to the external SPI slave.
b. Perform a read transaction from the next ROM and perform the same SPI write transaction to next
SPI slave.
2. Initialize the JESD204B IP base core, transport layer, pattern generator, and pattern checker upon
successful initialization of the transceiver.
UG-01142
2015.05.04
Finite State Machine (FSM)
5-39
JESD204B IP Core Design Guidelines
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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