Altera JESD204B IP User Manual Page 140
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Figure 6-1: Multi-Stage Pipeline Register for SYSREF Signal
Figure shows a two stages pipeline registers for the SYSREF signal.
SYSREF at
FPGA pin
D Q D Q D Q
User logic:
1
st
stage
pipeline
register
User logic:
2
nd
stage
pipeline
register
To IP core
internal logic
IP core register
rxlink_clk or
txlink_clk
Programmable RBD Offset
In the RX IP core, the programmable RBD offset provides flexibility for an early RBD release to optimize
the latency through the IP core. You can configure the RBD offset using the csr_rbd_offset field in the
syncn_sysref_ctrl register.
You should set a safe RBD offset value to ensure deterministic latency from one power cycle to another
power cycle. Follow these steps to set a safe RBD offset value:
1. Read the RBD count from the csr_rbd_count field in rx_status0 register. Record the value.
2. Power cycle the JESD204B subsystem, which consists of the FPGA and converter devices.
3. Read the RBD count again and record the value.
4. Repeat steps 1 to 3 at least 5 times and record the RBD count values.
5. Set the csr_rbd_offset accordingly with one LMFC count tolerance.
6. Perform multiple power cycles and make sure lane de-skew error does not occur using this RBD offset
value.
The RBD count should be fairly consistent, within 2 counts variation from one power cycle to another
power cycle. In the following examples, the parameter values are L > 1, F=1 and K=32. The legal values of
the LMFC counter is 0 to ((FxK/4)-1), which is 0 to 7. In Figure 6-2 , the latest arrival lane variation falls
within 1 local multi-frame period. In this scenario, if latency is not a concern, you can leave the default
value of csr_rbd_offset=0, which means the RBD elastic buffer is released at the LMFC boundary. In
Figure 6-3 , the latest arrival lane variation spans across 2 local multi-frames; the latest arrival lane
variation happens before and after the LMFC boundary. In this scenario, you need to configure the RBD
offset correctly to avoid lane de-skew error as indicated in bit 4 of rx_err0 register.
6-2
Programmable RBD Offset
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Deterministic Latency Implementation Guidelines
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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