Altera JESD204B IP User Manual Page 44
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Configura‐
tion Octet
Bits
Description
MSB 6 5 4 3 2 1 LSB
11 RES1[7:0] RES1 = Reserved. Set to 8'h00
12 RES2[7:0] RES2 = Reserved. Set to 8'h00
13 FCHK[7:0]; automatically calculated using run-time
configuration.
FCHK is the modulus 256 of the
sum of the 13 configuration octets
above.
If you change any of the octets
during run-time, make sure to
update the new FCHK value in the
register.
The JESD204 TX IP core also supports debug feature to continuously stay in ILAS phase without exiting.
You can enable this feature by setting the bit in csr_ilas_loop register. There are two modes of entry:
• RX asserts SYNC_N and deasserts it after CGS phase. This activity triggers the ILAS phase and the CSR
will stay in ILAS phase indefinitely until this setting changes.
• Link reinitialization through CSR is initiated. The JESD204B IP core transmits /K/ character and
causes the RX converter to enter CGS phase. After RX deasserts SYNC_N, the CSR enters ILAS phase
and will stay in that phase indefinitely until this setting changes.
In ILAS loop, the multi-frame transmission is the same where /R/ character (K28.0) marks the start of
multi-frame and /A/ character (K28.3) marks the end of multi-frame, with dummy data in between. The
dummy data is an increment of Dx.y.
User Data Phase
During the user data phase, character replacement at the end of frame and end of multi-frame is
opportunistically inserted so that there is no additional overhead for data bandwidth.
Character replacement for non-scrambled data
The character replacement for non-scrambled mode in the IP core follows these JESD204B specification
rules:
• At end of frame (not coinciding with end of multi-frame), which equals the last octet in the previous
frame, the transmitter replaces the octet with /F/ character (K28.7). However, if an alignment character
was transmitted in the previous frame, the original octet will be encoded.
• At the end of a multi-frame, which equals to the last octet in the previous frame, the transmitter
replaces the octet with /A/ character (K28.3), even if a control character was already transmitted in the
previous frame.
For devices that do not support lane synchronization, only /F/ character replacement is done. At every
end of frame, regardless of whether the end of multi-frame equals to the last octet in previous frame, the
transmitter encodes the octet as /F/ character (K28.7) if it fits the rules above.
UG-01142
2015.05.04
User Data Phase
4-7
JESD204B IP Core Functional Description
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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