Altera JESD204B IP User Manual Page 100
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Figure below illustrates the converter sample to transceiver lane mapping operation in the transport layer.
Each converter sample has N bits, M converters per ADC/DAC device, and S samples per converter (M)
per frame clock cycle. The transport layer operates at full rate or FRAMECLK_DIV=1.
1. The application layer or user logic data path interfaces directly with the transport layer through the
Avalon-ST data bus if the application layer operates in frame clock domain. If the application layer
operates at a different clock domain than the frame clock domain, add a FIFO for the clock domain
crossing.
2. You have to reorder the samples so that sample 0 of converter 0 is located at LSB of the Avalon-ST data
bus, followed by sample 1 of converter 0 (if S>1) or sample 0 of converter 1 (if S=1). The most signifi‐
cant bits (MSB) of the Avalon-ST bus has a sample of S -1 of converter M-1. For example, if S=4 and
M=4, the most significant bits will be occupied by sample 3 of converter 3.
3. In this example, there is no control word because CF=0. Control bits are added if CS>1. Depending on
the value of CS and N, the number of tail bits added is N'-N-CS. For example, N'=16, N=12 and CS=2,
the number of tail bits added to form a nibble group (NG) is 2.
4. The JESD204B IP core implements the data transfer in big endian format. Data is reshuffled in big
endian format before crossing to the link clock domain through an adaptor.
5. The data is arranged so that the L0 is always on the right (LSB) in the data bus interfacing with the
JESD204B IP core. In big endian implementation, the oldest data (F0) is placed at the MSB in L0. 32-
bits or 4 octets of data are transferred to the IP core in one link clock cycle. For example of F=8, 2 link
clock cycles are needed to transfer all 8 octets to the IP core.
UG-01142
2015.05.04
TX Path Data Remapping
5-19
JESD204B IP Core Design Guidelines
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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