Altera 100G Interlaken MegaCore Function User Manual

100G Interlaken MegaCore Function UserGuideLast updated for Altera Complete Design Suite: 15.0SubscribeSend FeedbackUG-011282015.05.04101 Innovation D

Related InformationAltera IP Core Release Notes1-6Release InformationUG-011282015.05.04Altera CorporationAbout This MegaCore FunctionSend Feedback

Specification, Revision 1.2. The TX Out-of-Band Flow Control Block Signals for Application Use tabledescribes the signals on the application side of t

RX Out-of-Band Flow Control SignalsThe receive out-of-band flow control interface receives input flow-control clock, data, and sync signalsand sends o

Signal Name Direction Width(Bits)Descriptioncalendar Output 16 Calendar bits received from an upstream out-of-bandTX block on fc_data.calendar_update

Performance and Fmax Requirements for 100GEthernet TrafficA2015.05.04UG-01128SubscribeSend FeedbackTo achieve 100G Ethernet line rates through the app

The following figures explain the derivation of the minimum frequency requirements.Figure A-2: Packet Processing Requirements in Single Segment Mode64

Table A-1: Packet Processing Time in Dual Segment Mode at 225 MHzThe time to process two consecutive packets at 225 MHz is simply the time taken by th

Additional InformationB2015.05.04UG-01128SubscribeSend FeedbackThis section provides additional information about the document and Altera.Document Rev

Date ACDSVersionChanges Made2014.12.15 14.1 • Updated release-specific information for the software release v14.1,including new resource utilization n

Date ACDSVersionChanges MadeDecember201313.1 Arria 10Edition(2013.12. 02)• Added preliminary support for Arria 10 devices.• Documented features of new

Date ACDSVersionChanges MadeMay 2013 13.0(2013.05.06)• Documented the new dual segment mode, including:• New Received data format parameter in the 100

Getting Started With the 100G Interlaken IPCore22015.05.04UG-01128SubscribeSend FeedbackThe following sections explain how to install, parameterize, s

How to Contact AlteraTable B-2: How to Contact AlteraTo locate the most up-to-date information about Altera products, refer to this table. You can als

Visual Cue MeaningItalic Type with Initial Capital Letters Indicate document titles. For example, Stratix VDesign Guidelines.italic type Indicates va

• Simulate the behavior of a licensed IP core in your system.• Verify the functionality, size, and speed of the IP core quickly and easily.• Generate

a. Click Finish. The Generation dialog box appears.b. Click Exit. The parameter editor adds the top-level .qsys file to the current project automatica

If you select the Verilog HDL for synthesis and simulation models, the demonstration testbench andexample design files are located in <your_ip>_

Figure 2-3: IP Core Generated Files<your_ip >.cmp - VHDL component declaration file<your_ip >.ppf - XML I/O pin information file<your

Simulating the100G Interlaken IP CoreYou can simulate your 100G Interlaken MegaCore function variation using any of the vendor-specificIEEE encrypted

Transceiver Logical Channel NumberingIn Arria V and Stratix V devices, logical channel numbering starts from zero. The logical channelnumbering starts

Transceiver Block Number Logical Channel Number inDeviceDirection Interlaken Lane Number inIP Core219TX17RX18TX16RX17TX15RX16TX14RX15TX13RX14TX12RX13

Transceiver Block Number Logical Channel Number inDeviceDirection Interlaken Lane Number inIP Core112TX11RX11TX10RX10TX9RX9TX8RX8TX7RX7TX6RX6 TX PLL 0

ContentsAbout This MegaCore Function... 1-1Features...

Transceiver Block Number Logical Channel Number inDeviceDirection Interlaken Lane Number inIP Core05TX5RX4TX4RX3TX3RX2TX2RX1TX1RX0TX0RXFor example, in

The following simple instructions show you how to instantiate an Altera Transceiver ReconfigurationController and how to connect the design blocks:Gen

Figure 2-4: Typical Connection of Reconfiguration Controller to 100G Interlaken IP Core100G InterlakenMegaCoreFunctionReconfigurationControllermgmt_cl

You must connect the external PLL signals and the Arria 10 100G Interlaken IP core transceiver Tx PLLinterface signals according to the following rule

• Pin Assignments on page 2-6• Arria 10 External PLL Interface Signals on page 5-15• Arria 10 Transceiver PHY User GuideInformation about the correspo

100G Interlaken IP Core Parameter Settings32015.05.04UG-01128SubscribeSend FeedbackYou customize the 100G Interlaken IP core by specifying parameters

Table 3-1: 100G Interlaken IP Core Supported Combinations of Number of Lanes and Data RateYes indicates a supported combination.Number of LanesLane Ra

If the actual frequency of the pll_ref_clk input clock does not match the value you specify for thisparameter, the design fails in both simulation and

Enable M20K ECC SupportThe Enable M20K ECC support parameter specifies whether your 100G Interlaken MegaCore functionvariation supports the ECC featur

• CRC24 Error Injection on page 8-8Include In-Band Flow Control BlockThe Include in-band flow control functionality parameter specifies whether your 1

Application Interface...4-1Interla

Transfer Mode SelectionThe Transfer mode selection parameter specifies whether the 100G Interlaken transmitter expectsincoming traffic to the TX user

Functional Description42015.05.04UG-01128SubscribeSend FeedbackThe 100G Interlaken MegaCore function provides the functionality described in the Inter

The 100G Interlaken MegaCore function value for the Interlaken BurstMax parameter is determined bythe value you specify on the burst_max_in input sign

Arria 10 Transceiver Reconfiguration Interface on page 4-3Transceiver Reconfiguration Controller Interface100G Interlaken IP core variations that targ

High Level Block DiagramFigure 4-1: 100G Interlaken Block Diagramirx_chan[7:0]irx_num_valid[7:0]irx_sob[1:0]irx_eobirx_sop[1:0]irx_eopbits[3:0]irx_dou

100G Interlaken IP Core Clock SignalsTable 4-1: 100G Interlaken IP Core ClocksClock Name Descriptionpll_ref_clkReference clock for the RX transceiver

Figure 4-2: 100G Interlaken IP Core Transceiver Initialization SequenceThe internal initialization sequence implemented by the reset controller includ

• Arria 10 Transceiver PHY User GuideFor more information about the Altera reset controller that is included in Arria 10 variations of the100G Interla

In Packet mode, the 100G Interlaken IP Core performs Optional Scheduling Enhancement based onSection 5.3.2.1.1 of the Interlaken Protocol Specificatio

You must enforce the following additional constraints in sending dual segment traffic to the TX user datatransfer interface:• The application can star

External Loopback Mode...8-2P

M20K ECC SupportIf you turn on Enable M20K ECC support in your Stratix V or Arria 10 100G Interlaken IP corevariation, the IP core takes advantage of

Figure 4-5: Packet Transfer on Transmit Interface in Interleaved Single Segment ModeThis example illustrates the expected behavior of the 100G Interla

data symbol contain valid data and the remaining words do not contain valid data, and that in the secondof these two words, only the three most signif

During the SOP cycle (labeled with data value d1) and the cycle that follows the SOP cycle (labeled withdata value d2), you must hold the value of itx

supports your design in achieving timing closure more easily. In any case you must ensure that you holditx_num_valid at the value of 0 when you are no

100G Interlaken IP Core Dual Segment Interleaved Data Transfer Transmit ExampleFigure 4-8: Dual Segment Data Transfer on Transmit Interface in Interle

In cycle 2, the following two events occur:• The first data burst completes. The application asserts itx_eob, indicating the data the applicationtrans

In dual segment mode as in single segment mode, if the IP core is in Interleaved mode, you can transfer apacket without interleaving—if you do not tog

Control Word Reset Calendar Bit (bit [56]) In-Band Flow Control Bits (bits [55:40])Second 0 16'b0010001000100010 (16'h2222)Third 0 16'b

100G Interlaken IP Core TX MAC on page 4-19100G Interlaken IP Core TX PCS on page 4-19100G Interlaken IP Core TX PMA on page 4-19100G Interlaken IP Co

About This MegaCore Function12015.05.04UG-01128SubscribeSend FeedbackInterlaken is a high-speed serial communication protocol for chip-to-chip packet

100G Interlaken IP Core Receive User Data Interface ExamplesThe following examples illustrate how to use the Altera 100G Interlaken IP core RX user da

4'b1011 on irx_eopbits to indicate that the data the IP core transfers to the application in this cycle arethe final words of the packet, and tha

100G Interlaken IP Core Dual Segment Interleaved Data Transfer Receive ExampleFigure 4-11: Dual Segment Data Transfer on Receive Interface in Interlea

In cycle 2, the following two events occur:• The first data burst completes. The IP core asserts irx_eob, indicating the data the IP core transfers to

packet transfer, the packet is not interleaved with another packet. In this case, the IP core still asserts theirx_sob and irx_eob signals correctly t

application can rely on the fact that if irx_err is not asserted and irx_eopbits has a value other than4'b0001, the packet is not errored.For CRC

following clock cycle, labeled with data value d3, the 100G Interlaken IP Core holds the following valueson critical output signals:• itx_num_valid[7:

100G Interlaken IP Core Receive Path BlocksFigure 4-13: 100G Interlaken IP Core Receive Pathirx_chan[7:0]irx_num_valid[7:0]irx_sob[1:0]irx_eobirx_sop[

The 100G Interlaken MegaCore function RX MAC performs the following functions:• Data de-striping, including lane alignment and burst assembly from the

100G Interlaken MegaCore Function Signals52015.05.04UG-01128SubscribeSend FeedbackThe 100G Interlaken MegaCore function communicates with the surround

• Supports Packet mode and Interleaved (Segmented) mode for user data transfer.• Supports dual segment mode for efficient user data transfer.• Support

Signal Name Direction Width(Bits)Descriptiontx_serial_clkInputNUM_LANES–Clocks for the individual transceiver channels in100G Interlaken IP core varia

100G Interlaken IP Core Reset Interface SignalsTable 5-3: 100G Interlaken IP Core Reset InterfaceSignal Name Direction Width(Bits)Description100G Inte

100G Interlaken IP Core User Data Transfer Interface SignalsTable 5-4: 100G Interlaken IP Core User Data Transfer InterfaceSignal Name Direction Width

Signal Name Direction Width(Bits)Descriptionitx_eopbitsInput 4 Indicates whether the current data symbol contains the end of a packet(EOP) with or wit

Signal Name Direction Width(Bits)Descriptionitx_calendarInput 16 N Multiple pages (16 bits per page) of calendar input bits. The100G Interlaken IP Cor

Signal Name Direction Width(Bits)Descriptionirx_num_validOutput 8 irx_num_valid[7:4] specifies the number of valid 64-bit words in thecurrent packet i

Signal Name Direction Width(Bits)Descriptionirx_eopbitsOutput 4 Indicates whether the current data symbol contains the end of a packet(EOP) with or wi

Signal Name Direction Width(Bits)Descriptionirx_err Output 1Indicates an errored packet. This signal is valid only when bothirx_num_valid[7:4] and irx

Signal Name Direction Width (Bits) Descriptionburst_max_in Input 4 Encodes the BurstMax parameter for the IPcore. The actual value of the BurstMaxpara

Signal Name Direction Width (Bits) Descriptiontx_lanes_alignedOutput 1 All of the transmitter lanes are aligned and areready to send traffic.itx_hungr

FPGA Device FamiliesFinal support — The IP core is verified with final timing models for this device family. The IP core meets allfunctional and timin

Signal Name Direction Width (Bits) Descriptioncrc24_err Output 1 A CRC24 error flag covering both control wordand data word. This signal does not asso

Related InformationRXFIFO Address Width on page 9-2Information about programming the depth of the Reassembly FIFO with the RXFIFO_ADDR_WIDTHparameter.

If you use the management interface, drive the control lines as shown in the examples and observing thefollowing constraints:• During a write operatio

requirements to support the Arria 10 transceivers. The following 100G Interlaken IP core interfaces aredevice specific:Transceiver Reconfiguration Con

Table 5-8: 100G Interlaken IP Core Arria 10 External PLL Interface SignalsSignal Name Direction Width (Bits) Descriptiontx_serial_clk Input NUM_LANES

Signal Name Direction Width(Bits)Descriptionreconfig_address Input 14 or 15 Address to access the hard PCS registers. This signalholds both the hard P

100G Interlaken IP Core Register Map62015.05.04UG-01128SubscribeSend FeedbackThe 100G Interlaken IP core control registers are 32 bits wide and are ac

Offset Name R/W Description9'h4 TX_EMPTY RO [NUM_LANES–1:0] – Transmit FIFO status (empty)9'h5 TX_FULL RO [NUM_LANES–1:0] – Transmit FIFO st

Offset Name R/W Description9'h10PLL_LOCKEDRO In Arria 10 devices: [0] – Transmit PLL lock indication.In other device families: [Number of transce

Offset Name R/W Description9'h23CRC0RO 4 bit counters indicating CRC errors in lanes 7,6,5,4,3,2,1,0.These will saturate at F, and you clear them

Table 1-5: 100G Interlaken MegaCore Function FPGA Resource Utilization Lists the resources and expected performance for selected variations of the 100

Offset Name R/W Description9'h31PCS_LNSELRO Lane selection within transceiver block for PCS test bus.(Factory use only).If you turn off Include d

Offset Name R/W Description9'h102ERR_INJECTRW Bit [0] - When you write the value of 1 to this register bit,the IP core TX MAC injects a single bi

100G Interlaken IP Core Testbench72015.05.04UG-01128SubscribeSend FeedbackWhen you generate an 100G Interlaken IP core variation with Verilog HDLsynth

In Arria 10 variations, the example design includes external TX PLLs. You can examine the clear text filesto view sample code that implements one poss

Note: If the IP core is in dual segment mode, the testbench sends 65-byte bursts on the TX user datatransfer interface. If the IP core is in single se

packets that the IP core generates on the RX user data transfer interface. After simulation completes, asuccess or failure notice displays.7-4Simulati

100G Interlaken IP Core Test Features82015.05.04UG-01128SubscribeSend FeedbackDepending on the features you turn on in the 100G Interlaken parameter e

External Loopback ModeThe 100G Interlaken IP core operates correctly in an external loopback configuration.To put the IP core in external loopback mod

This section describes the register values you must program. For instructions to program the registers thatactivate the PRBS test feature in your Arri

RX Register Offset Bits Meaning Action3 0x164 [10] Enable RX PRBS clock Set this bit to the value of 1 to enable theRX PRBS clock.After you activate a

Device Speed Grade SupportTable 1-6: Minimum Recommended Device Family Speed Grades For each device family the 100G Interlaken IP core supports, Alter

Table 8-3: Programming the Hard PCS Registers in Arria 10 DevicesTo turn on the PRBS feature in the hard PCS for IP core variations that target an Arr

RX Register Offset Bits Meaning Action2 0xB[1]Enable 10G PCS mode Set this bit to the value of 1 to specify thePCS is in 10G mode.[3:2] Verifier count

Related Information• 100G Interlaken IP Core Register Map on page 6-1Describes the PRBS status registers and the soft reset register.• Arria 10 Transc

CRC24 Error InjectionThe 100G Interlaken IP core supports the injection of CRC24 errors on the Interlaken link for validationof the Interlaken link pa

Advanced Parameter Settings92015.05.04UG-01128SubscribeSend FeedbackAdvanced users can further customize the 100G Interlaken IP core by modifying hidd

RXFIFO Address WidthThe RXFIFO Address Width parameter specifies the number of bits in the address (offset) of an entry inthe RX Reassembly FIFO. The

Figure 9-2: Swapped Lane OrderLane 1Lane 2Lane 0...Lane NTwo parameters determine lane order:SWAP_TX_LANESSWAP_RX_LANESWhen a parameter is set to 0, t

Parameter Arria 10 Variations Other VariationsSWAP_TX_LANESSWAP_RX_LANES<instance name>/ilk_core_<version>/synth/ilk_core.sv<instance n

Out-of-Band Flow Control in the100G Interlaken MegaCore Function102015.05.04UG-01128SubscribeSend FeedbackThe 100G Interlaken MegaCore function includ

Related InformationInterlaken Protocol Specification, Revision 1.2Out-of-Band Flow Control Block ClocksTable 10-1: 100G Interlaken MegaCore Function O