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JESD204B IP Core Debug Guidelines
7
2015.05.04
UG-01142
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This section lists some guidelines to assist you in debugging JESD204B link issues. Apart from applying
general board level hardware troubleshooting technique like checking the power supply, external clock
source, physical damage on components, a fundamental understanding of the JESD204B subsystem
operation is important.
Related Information
• Clocking Scheme on page 7-1
• JESD204B Parameters on page 7-1
• SPI Programming on page 7-2
• Converter and FPGA Operating Conditions on page 7-2
• Signal Polarity and FPGA Pin Assignment on page 7-2
• Debugging JESD204B Link Using SignalTap II and System Console on page 7-3
Clocking Scheme
To verifying the clocking scheme, follow these steps:
1. Check that the frame and link clock frequency settings are correct in the Altera PLL IP core. For the
design example, the frame clock is assigned to outclk0 and link clock is assigned to outclk1.
2. Check the device clock frequency at the FPGA and converter.
3. For Subclass 1, check the SYSREF pulse frequency.
4. Check the clock frequency management. For the design example, using Stratix V and Arria V devices,
this frequency is 100 MHz.
JESD204B Parameters
The parameters in both the FPGA and ADC should be set to the same values. For example, when you set
K = 32 on the FPGA, set the converter's K value to 32 as well. Scrambling does not affect the link initiali‐
zation in the CGS and ILAS phases but in the user data phase. When scrambling is enabled on the ADC,
the FPGA descrambling option has to be turned on using the "Enable scramble (SCR)" option in the
JESD204B IP core Qsys parameter editor. When scrambling is enabled on the FPGA, the DAC descram‐
bling has to be turned on too.
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trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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