Altera SCFIFO User Manual

SCFIFO and DCFIFO IP Cores User Guide2014.12.17UG-MFNALT_FIFOSubscribeSend FeedbackAltera provides FIFO functions through the parameterizable single-c

Parameter Type RequiredDescriptionadd_ram_output_register String No Specifies whether to register the q output. The valuesare ON and OFF. If omitted,

Figure 2: Functional Timing for the wrreq Signal and the wrfull SignalThis figure shows the behavior for the wrreq and the wrfull signals.Figure 3: Fu

Table 4: Output Latency of the Status Flags for SCFIFOThis table shows the output latency of the write signal (wrreq) and read signal (rdreq) for the

Table 5: LE Implemented RAM Mode for SCFIFO and DCFIFOOutput Mode Optimization Option (10)Output Latency (in number of clock cycles) (11)Normal (12)Sp

Table 6: Output Latency of the Status Flag for the DCFIFOThis table shows the output latency of the write signal (wrreq) and read signal (rdreq) for t

Group Setting CommentMinimal setting for unsynchronized clocks This option uses two synchronization stages withgood metastability protection. It uses

SCFIFO and DCFIFO Synchronous Clear and Asynchronous Clear EffectThe FIFO IP cores support the synchronous clear (sclr) and asynchronous clear (aclr)

Table 10: Asynchronous Clear in DCFIFOThis table shows the asynchronous clear supported by the DCFIFO.Mode Asynchronous Clear(aclr)aclr (synchronizewi

Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO IPCoreDuring compilation of a design that contains a DCFIFO IP core, the Quartu

Figure 5: Writing 8-Bit Words and Reading 16-Bit WordsThis figure shows an example of a narrow write port (8-bit input) with a wide read port (16-bit

SpecificationsVerilog HDL PrototypeYou can locate the Verilog HDL prototype in the Verilog Design File (.v) altera_mf.v in the <Quartus IIinstallat

register. To ensure the q output is valid, sample the output only after the rdempty signal isdeasserted.Related InformationQuartus II TimeQuest Timing

Design ExampleIn this design example, the data from the ROM is required to be transferred to the RAM. Assuming theROM and RAM are driven by non-relate

Figure 7: Initial Write Operation to the DCFIFO IP CoreTable 12: Initial Write Operation to the DCFIFO IP Core Waveform DescriptionState DescriptionID

Figure 8: Initial Read Operation from the DCFIFO IP CoreTable 13: Initial Read Operation from the DCFIFO IP Core Waveform DescriptionState Description

Figure 9: Write Operation when DCFIFO is FULLTable 14: Write Operation when DCFIFO is FULL Waveform DescriptionState DescriptionINCADRWhen the write c

Table 15: Completion of Data Transfer from ROM to DCFIFO Waveform DescriptionState DescriptionWRITE When the write controller is in the WRITE state, a

Gray-Code Counter Transfer at the Clock Domain CrossingThis section describes the effect of the large skew between Gray-code counter bits transfers at

Table 16: Document Revision HistoryDate Version ChangesDecember 2014 2014.12.17• Clarified that there are no minimum number ofclock cycles for aclr si

Date Version ChangesJanuary 2010 6.1• Updated “Functional Timing Requirements”section.• Minor changes to the text.September 2009 6.0• Replaced “FIFO M

Table 2: Input and Output Ports DescriptionThis table lists the signals of the IP cores. The term “series” refers to all the device families of a part

Port Type Required Descriptionwrreq (3)Input Yes Assert this signal to request for a write operation.Ensure that the following conditions are met:• Do

Port Type Required Descriptionq (3)Output Yes Shows the data read from the read request operation.For the SCFIFO IP core and DCFIFO IP core, the wid

Port Type Required Descriptionusedw (1)wrusedw (2), (4)rdusedw (2), (4)Output No Show the number of words stored in the FIFO.Ensure that the port wi

Parameter Type RequiredDescriptionlpm_numwords Integer Yes Specifies the depths of the FIFO you require. The valuemust be at least 4.The value assigne

Parameter Type RequiredDescriptiondelay_rdusedw (5)delay_wrusedw(5)String No Specify the number of register stages that you want tointernally add to t

Parameter Type RequiredDescriptionwrite_aclr_synch(5)String No Specifies whether or not to add a circuit that causes theaclr port to be internally syn