Altera JESD204B IP User Manual Page 31
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Parameter Value Description
Data Path
• Receiver
• Transmitter
• Duplex
Select the operation modes. This selection enables or disables
the receiver and transmitter supporting logic.
• RX—instantiates the receiver to interface to the ADC.
• TX—instantiates the transmitter to interface to the DAC.
• Duplex—instantiates the receiver and transmitter to
interface to both the ADC and DAC.
JESD204B Subclass • 0
• 1
• 2
Select the JESD204B subclass modes.
• 0—Set subclass 0
• 1—Set subclass 1
• 2—Set subclass 2
Data Rate 1.0–12.5 Set the data rate for each lane.
(12)
• Cyclone V—1.0 Gbps to 5.0 Gbps
• Arria V—1.0 Gbps to 6.55 Gbps
• Arria V GZ—2.0 Gbps to 9.9 Gbps
• Arria 10—2.0 Gbps to 12.5 Gbps
• Stratix V—2.0 Gbps to 12.5 Gbps
PCS Option • Enabled
Hard PCS
• Enabled Soft
PCS
Select the PCS modes.
• Enabled Hard PCS—utilize Hard PCS components. Select
this option to minimize resource utilization with data rate
that supports up to the limitation of the Hard PCS.
Note: For this setting, you will utilize 8G PCS mode
with 20 bits PMA width and 32 bits PCS width.
• Enabled Soft PCS—utilize Soft PCS components. Select this
option to allow higher supported data rate but increase in
resource utilization.
Note: For this setting, you will utilize 10G PCS mode
with 40 bits PMA width and 40 bits PCS width.
PLL Type • CMU
• ATX
Select the Phase-Locked Loop (PLL) types, depending on the
FPGA device family.
• Cylone V—CMU
• Arria V—CMU
• Stratix V—CMU, ATX
(12)
The maximum data rate is limited by different device speed grade, transceiver PMA speed grade, and
PCS options. Refer to Table 3-4 for the maximum data rate support.
UG-01142
2015.05.04
JESD204B IP Core Parameters
3-17
Getting Started
Altera Corporation
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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