Altera DE2-115 User Manual download pdf (Page 49)

Table 4-11 Voltage Level Setting of the Expansion Headers Using JP6

JP6 Jumper Settings Supplied Voltage to VCCIO4 IO Voltage of Expansion Headers (JP5)

Short Pins 1 and 2 1.5V 1.5V

Short Pins 3 and 4 1.8V 1.8V

Short Pins 5 and 6 2.5V 2.5V

Short Pins 7 and 8 3.3V 3.3V (Default)

Note : Users who want to use daughter card on GPIO connector need to pay close attention to the

I/O standard between DE2-115 GPIO connector pins and daughter card system. For example, if the I/O

standard of GPIO pins on DE2-115 board is set to 1.8V, a daughter card with 3.3V I/O standard may not

work properly on the DE2-115 board due to I/O standard mismatch.

Figure 4-18 depicts the pin definition on the expansion connector for using these I/Os as LVDS

transmitters. Due to the reason that the column I/Os of the FPGA the expansion pins connecting

with can only support emulated LVDS transmitters, two single-ended output buffers and external

resistors must be used as shown in Figure 4-19. The associated I/O standard of these differential

FPGA I/O pins on Quartus II project should set to LVDS_E_3R.

Figure 4-18 Pin defined when using LVDS interface on GPIO FPGA pins

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Altera DE2-115 User Manual Page 49