Altera DE2-115 User Manual download pdf (Page 31)

JTAG chain on DE2-115 board. Shorting pin1 and pin2 on JP3 can disable the JTAG signals on

HSMC connector that will form a close JTAG loop chain on DE2-115 board (See Figure 4-2). Thus,

only the on board FPGA device (Cyclone IV E) will be detected by Quartus II programmer. If users

want to include another FPGA device or interface containing FPGA device in the chain via HSMC

connector, short pin2 and pin3 on JP3 to enable the JTAG signal ports on the HSMC connector.

Figure 4-1 The JTAG chain on DE2-115 board

Figure 4-2 The JTAG chain configuration header

The sections below describe the steps used to perform both JTAG and AS programming. For both

methods the DE2-115 board is connected to a host computer via a USB cable. Using this connection,

the board will be identified by the host computer as an Altera USB Blaster device. The process for

installing on the host computer the necessary software device driver that communicates with the

USB Blaster is described in the tutorial “Getting Started with Altera’s DE2-115 Board”

(tut_initialDE2-115.pdf). This tutorial is available on the DE2-115 System CD.

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Altera DE2-115 User Manual Page 31