Altera DE2-115 User Manual download pdf (Page 61)

Figure 4-29 Connections between FPGA and TV Decoder

Note: If the HSMC loopback adapter is mounted, the I2C_SCL will be directly routed back to I2C_SDA.

Because audio chip, TV decoder chip and HSMC share one I2C bus, therefore audio and video chip won’t

function correctly.

Table 4-24 TV Decoder Pin Assignments

Signal Name FPGA Pin No. Description I/O Standard

TD_ DATA [0] PIN_E8 TV Decoder Data[0] 3.3V

TD_ DATA [1] PIN_A7 TV Decoder Data[1] 3.3V

TD_ DATA [2] PIN_D8 TV Decoder Data[2] 3.3V

TD_ DATA [3] PIN_C7 TV Decoder Data[3] 3.3V

TD_ DATA [4] PIN_D7 TV Decoder Data[4] 3.3V

TD_ DATA [5] PIN_D6 TV Decoder Data[5] 3.3V

TD_ DATA [6] PIN_E7 TV Decoder Data[6] 3.3V

TD_ DATA [7] PIN_F7 TV Decoder Data[7] 3.3V

TD_HS PIN_E5 TV Decoder H_SYNC 3.3V

TD_VS PIN_E4 TV Decoder V_SYNC 3.3V

TD_CLK27 PIN_B14 TV Decoder Clock Input. 3.3V

TD_RESET_N PIN_G7 TV Decoder Reset 3.3V

I2C_SCLK PIN_B7 I2C Clock 3.3V

I2C_SDAT PIN_A8 I2C Data 3.3V

1 2 ... 56 57 58 59 60 61 62 63 64 65 66 ... 120 121

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Altera DE2-115 User Manual Page 61