80
necessary (that is, if the default factory configuration of the DE2-115 board is not currently
stored in EPCS64 device), download the bit stream to the board by using either JTAG or AS
programming
• You should now be able to observe that the 7-segment displays are displaying a sequence of
characters, and the red and green LEDs are flashing. Also, “Welcome to the Altera DE2-115” is
shown on the LCD display
• Optionally connect a VGA display to the VGA D-SUB connector. When connected, the VGA
display should show a color picture
• Optionally connect a powered speaker to the stereo audio-out jack
• Place slide switch SW17 in the DOWN position to hear a 1 kHz humming sound from the
audio-out port. Alternatively, if slide switch SW17 is in the UP position, and optionally connects
the microphone in port with a microphone and/or connects the line-in port with an audio
player’s output, you will hear the sound from the microphone or audio player or mixed sound
from both.
The Verilog HDL source code for this demonstration is provided in the DE2_115_Default folder,
which also includes the necessary files for the corresponding Quartus II project. The top-level
Verilog HDL file, called DE2_115_Default.v, can be used as a template for other projects, because it
defines ports that correspond to all of the user-accessible pins on the Cyclone IV E FPGA.
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This demonstration plays video and audio input from a DVD player using the VGA output, audio
CODEC, and one TV decoder (U6) on the DE2-115 board. Figure 6-1 shows the block diagram of
the design. There are two major blocks in the circuit, called I2C_AV_Config and TV_to_VGA. The
TV_to_VGA block consists of the ITU-R 656 Decoder, SDRAM Frame Buffer, YUV422 to
YUV444, YcrCb to RGB, and VGA Controller. The figure also shows the TV Decoder (ADV7180)
and the VGA DAC (ADV7123) chips used.
As soon as the bit stream is downloaded into the FPGA, the register values of the TV Decoder chip
are used to configure the TV decoder via the I2C_AV_Config block, which uses the I2C protocol to
communicate with the TV Decoder chip. Following the power-on sequence, the TV Decoder chip
will be unstable for a time period; the Lock Detector is responsible for detecting this instability.
The ITU-R 656 Decoder block extracts YcrCb 4:2:2 (YUV 4:2:2) video signals from the ITU-R 656
data stream sent from the TV Decoder. It also generates a data valid control signal indicating the
valid period of data output. Because the video signal from the TV Decoder is interlaced, we need to
perform de-interlacing on the data source. We used the SDRAM Frame Buffer and a field selection
multiplexer (MUX) which is controlled by the VGA controller to perform the de-interlacing
operation. Internally, the VGA Controller generates data request and odd/even selection signals to
the SDRAM Frame Buffer and filed selection multiplexer (MUX). The YUV422 to YUV444 block
converts the selected YcrCb 4:2:2 (YUV 4:2:2) video data to the YcrCb 4:4:4 (YUV 4:4:4) video
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