Altera DE2-115 User Manual download pdf (Page 62)

Although the DE2-115 board does not include a TV encoder chip, the ADV7123 (10-bit high-speed

triple ADCs) can be used to implement a professional-quality TV encoder with the digital

processing part implemented in the Cyclone IV E FPGA. Figure 4-30 shows a block diagram of a

TV encoder implemented in this manner.

Figure 4-30 A TV Encoder that uses the Cyclone IV E FPGA and the ADV7123

The DE2-115 board provides both USB host and device interfaces using the Cypress EZ-OTG

(CY7C67200) On-The-Go (OTG) host/peripheral controller. The host and device controllers are

compliant with the Universal Serial Bus Specification Rev. 2.0, supporting data transfer at

full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). Figure 4-31 shows the schematic diagram of the

USB circuitry. The interface between CY7C67200 and FPGA is set to Host Port Interface (HPI)

which can provide DMA access to the CY7C67200 internal memory by FPGA, plus a bidirectional

mailbox register for supporting high-level communication protocols. Also the pin assignments for

the associated interface are listed in Table 4-25.

Detailed information for using the CY7C67200 device is available in its datasheet and

programming guide; both documents can be found on the manufacturer’s website, or in the

DE2_115_datasheets\USB folder on the DE2-115 System CD. The most challenging part of a USB

application is in the design of the software driver needed. Two complete examples of USB drivers,

for both host and device applications, can be found in Sections 6.4 and 6.5. These demonstrations

provide examples of software drivers for the Nios II processor.

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Altera DE2-115 User Manual Page 62