Altera DE2-115 User Manual download pdf (Page 55)

(Encoder/Decoder). This chip supports microphone-in, line-in, and line-out ports, with a sample rate

adjustable from 8 kHz to 96 kHz. The WM8731 is controlled via serial I2C bus interface*, which is

connected to pins on the Cyclone IV E FPGA. A schematic diagram of the audio circuitry is shown

in Figure 4-23, and the FPGA pin assignments are listed in Table 4-17. Detailed information for

using the WM8731 codec is available in its datasheet, which can be found on the manufacturer’s

website, or in the DE2_115_datasheets\Audio CODEC folder on the DE2-115 System CD.

Figure 4-23 Connections between FPGA and Audio CODEC

Table 4-17 Audio CODEC Pin Assignments

Signal Name FPGA Pin No. Description I/O Standard

AUD_ADCLRCK PIN_C2 Audio CODEC ADC LR Clock 3.3V

AUD_ADCDAT PIN_D2 Audio CODEC ADC Data 3.3V

AUD_DACLRCK PIN_E3 Audio CODEC DAC LR Clock 3.3V

AUD_DACDAT PIN_D1 Audio CODEC DAC Data 3.3V

AUD_XCK PIN_E1 Audio CODEC Chip Clock 3.3V

AUD_BCLK PIN_F2 Audio CODEC Bit-Stream Clock 3.3V

I2C_SCLK PIN_B7 I2C Clock 3.3V

I2C_SDAT PIN_A8 I2C Data 3.3V

Note: If the HSMC loopback adapter is mounted, the I2C_SCL will be directly routed back to I2C_SDA.

Because audio chip, TV decoder chip and HSMC share one I2C bus, therefore audio and video chip won’t

function correctly.

The DE2-115 board uses the ZT3232 transceiver chip and a 9-pin DB9 connector for RS-232

communications. For detailed information on how to use the transceiver, please refer to the

datasheet, which is available on the manufacturer’s website, or in the DE2_115_datasheets\RS-232

folder on the DE2-115 System CD. Figure 4-24 shows the related schematics, and Table 4-18 lists

the Cyclone IV E FPGA pin assignments.

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Altera DE2-115 User Manual Page 55