Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual Page 82
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Bits Register Description Reset Value Access
[1] START_XFER. Sets the CvP output to the FPGA control block
indicating the start of a transfer.
1’b0 RW
[0] CVP_CONFIG. When asserted, instructs that the FPGA control
block begin a transfer via CvP.
1’b0 RW
64- or 128-Bit Avalon-MM Bridge Register Descriptions
The CRA Avalon-MM slave module provides access control and status registers in the PCI Express
Avalon-MM bridge. In addition, it provides access to selected Configuration Space registers and link
status registers in read-only mode. This module is optional. However, you must include it to access the
registers.
The control and status register address space is 16 KBytes. Each 4-KByte sub-region contains a set of
functions, which may be specific to accesses from the PCI Express Root Complex only, from Avalon-MM
processors only, or from both types of processors. Because all accesses come across the interconnect fabric
—requests from the Avalon-MM Stratix V Hard IP for PCI Express are routed through the interconnect
fabric—hardware does not enforce restrictions to limit individual processor access to specific regions.
However, the regions are designed to enable straight-forward enforcement by processor software. The
following figure illustrates accesses to the Avalon-MM control and status registers from the Host CPU
and PCI Express link.
Figure 5-9: Accesses to the Avalon-MM Bridge Control and Status Register
Transaction,
Data Link,
and PHY
Qsys Generated Endpoint (Altera FPGA)
PCI Express Avalon-MM Bridge
Interconnect
Avalon-MM Hard IP for PCI Express
Control and Status Registers
Control Register Access (CRA)
PCIe TLP Address
RX
PCIe
Link
0x0000-0x0FFF: PCIe processors
0x1000-0x1FFF: Addr translation
0x2000-0x2FFF: Root Port TLP Data
0x3000-0x3FFF: Avalon-MM processors
Host
CPU
Avalon-MM
32-Bit Byte Address
Avalon-MM Slave
UG-01097_avmm
2014.12.15
64- or 128-Bit Avalon-MM Bridge Register Descriptions
5-13
Registers
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
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