Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual

Stratix V Avalon-MM Interface for PCIe SolutionsUser GuideSubscribeSend FeedbackLast updated for Altera Complete Design Suite: 14.1 UG-01097_avmm2014.

Debug FeaturesDebug features allow observation and control of the Hard IP for faster debugging of system-levelproblems.Related InformationDebugging on

Figure 5-12: Root Port TLP Data RegistersRX_TX_CNTLRP_RXCPL_REG0RP_RXCPL_REGRP_RXCPL_STATUSControlRegisterAccessSlaveAvalon-MMMaster32323232646432IRQR

Root-Port Request Registers Address Range: 0x2800-0x2018Address Bits Name Access Description0x2010[31:16] Reserved — —[15:8]RP_RXCPL_STATUSR Specifies

Bits Register Description Reset Value Access[11] Mask for RX buffer posted and completion overflow error. 1b’1 RWS[10] Reserved 1b’0 RO[9] Mask for pa

Bits Register DescriptionResetValueAccess[10] Reserved.0RO[9] When set, indicates a parity error was detected on the Configu‐ration Space to TX bus in

Bits Register Description Reset Value Access[6] Mask for Corrected Internal Error reported by the ApplicationLayer.1 RWS[5] Mask for configuration err

Reset and Clocks62014.12.15UG-01097_avmmSubscribeSend FeedbackStratix V Hard IP for PCI Express IP Core includes both a soft reset controller and a ha

Figure 6-1: Reset Controller Block DiagramExample Designaltpcie_dev_hip_<if>_hwtcl.valtpcied_<dev>_hwtcl.svTransceiver HardReset Logic/Sof

Reset Sequence for Hard IP for PCI Express IP Core and Application LayerFigure 6-2: Hard IP for PCI Express and Application Logic Reset SequenceYour A

Figure 6-3: RX Transceiver Reset Sequencebusy_xcvr_reconfigrx_pll_lockedrx_analogresetltssmstate[4:0]txdetectrx_loopbackpipe_phystatuspipe_rxstatus[2:

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.ClocksThe Hard IP contains a clock domain c

Table 1-5: Performance and Resource Utilization Avalon-MM Hard IP for PCI ExpressInterface Width ALMs M20K Memory Blocks Logic RegistersAvalon-MM Brid

The PCI Express Base Specification requires that the refclk signal frequency be 100 MHz ±300 PPM.The transitions between Gen1, Gen2, and Gen3 should b

Link Width Maximum Link Rate Avalon Interface Width coreclkout_hip×1Gen2 64125 MHz×2Gen2 64125 MHz×4 Gen2 64 250 MHz×4 Gen2 128 125 MHz×8 Gen2 128 250

Clock SummaryTable 6-4: Clock SummaryName Frequency Clock Domaincoreclkout_hip62.5, 125 or 250 MHz Avalon-ST interface between the Transaction andAppl

Interrupts for Endpoints72014.12.15UG-01097_avmmSubscribeSend FeedbackThe PCI Express Avalon-MM bridge supports MSI or legacy interrupts. The complete

Figure 7-1: Avalon-MM Interrupt Propagation to the PCI Express LinkInterrupt Disable(Configuration Space Command Register [10])Avalon-MM-to-PCI-Expres

Generation of Avalon-MM InterruptsThe generation of Avalon-MM interrupts requires the instantiation of the CRA slave module where theinterrupt registe

Figure 7-2: Block Diagram for Custom Interrupt HandlerMSMSI/MSI-X IRQMSI-X Table EntriesSQsysInterconnectSMPCIe-Avalon-MMBridgeHardIP forPCIeMSI orMSI

Error Handling82014.12.15UG-01097_avmmSubscribeSend FeedbackEach PCI Express compliant device must implement a basic level of error management and can

Physical Layer ErrorsTable 8-2: Errors Detected by the Physical LayerThe following table describes errors detected by the Physical Layer. Physical Lay

Transaction Layer ErrorsTable 8-4: Errors Detected by the Transaction LayerError Type DescriptionPoisoned TLP received Uncorrectable(non-fatal)This er

Related Information• Area and Timing Optimization• Altera Software Installation and Licensing Manual• Setting up and Running Analysis and SynthesisSte

Error Type DescriptionIn all cases the TLP is deleted in the Hard IP block andnot presented to the Application Layer. If the TLP is anon-posted reques

Error Type DescriptionUnexpected completion Uncorrectable(non-fatal)This error is caused by an unexpected completiontransaction. The Hard IP block han

Error Type DescriptionMalformed TLP Uncorrectable(fatal)This error is caused by any of the following conditions:• The data payload of a received TLP e

Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status register.Table 8-5: Parity Error ConditionsStatus Bit Condition

Figure 8-2: Correctable Error Status RegisterThe default value of all the bits of this register is 0. An error status bit that is set indicates that t

IP Core Architecture92014.12.15UG-01097_avmmSubscribeSend FeedbackThe Avalon-MM Stratix V Hard IP for PCI Express implements the complete PCI Express

Figure 9-1: Stratix V Hard IP for PCI Express Using the Avalon-MM InterfaceClockDomainCrossing(CDC)Data LinkLayer(DLL)Transaction Layer (TL)PHYMAC Har

Top-Level InterfacesAvalon-MM InterfaceAn Avalon-MM interface connects the Application Layer and the Transaction Layer. The Avalon-MMinterface impleme

PIPEThe PIPE interface implements the Intel-designed PIPE interface specification. You can use this parallelinterface to speed simulation; however, yo

Figure 9-2: Data Link LayerTo Transaction LayerTx Transaction LayerPacket Description & DataTransaction LayerPacket GeneratorRetry BufferTo Physic

Getting Started with the Avalon‑MM Stratix VHard IP for PCI Express22014.12.15UG-01097_avmmSubscribeSend FeedbackYou can download a design example for

• ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequencenumber of transmitted packets.• Transaction Layer Packet Checker—T

Figure 9-3: Physical Layer ArchitectureScrambler8B10BEncoderLane nTX+ / TX-Scrambler8B10BEncoderLane 0TX+ / TX-Descrambler8B10BDecoderLane nRX+ / RX-E

The PHYMAC block comprises four main sub-blocks:• MAC Lane—Both the RX and the TX path use this block.• On the RX side, the block decodes the Physical

The Avalon-MM bridge provides three possible Avalon-MM ports: a bursting master, an optionalbursting slave, and an optional non-bursting slave. The Av

Figure 9-4: PCI Express Avalon-MM BridgeTransaction LayerPCI ExpressTx ControllerPCI ExpressRx ControllerData Link LayerPhysical LayerPCI Express Mega

Related InformationAvalon-MM RX Master Block on page 9-20Avalon‑MM Bridge TLPsThe PCI Express to Avalon-MM bridge translates the PCI Express read, wri

PCI Express-to-Avalon-MM Read CompletionsThe PCI Express Avalon-MM bridge returns read completion packets to the initiating Avalon-MMmaster in the iss

Related InformationMinimizing BAR Sizes and the PCIe Address Space on page 9-15Avalon-MM-to-PCI Express Read CompletionsThe PCI Express Avalon-MM brid

Figure 9-5: Address Translation in TX and RX Directions For EndpointsTransaction,Data Link,and PHYDMAAvalon-MM32-Bit Byte AddressAvalon-MM32-Bit Byte

Minimizing BAR Sizes and the PCIe Address SpaceFor designs that include multiple BARs, you may need to modify the base address assignmentsauto-assigne

The design example transfers data between an on-chip memory buffer located on the Avalon-MM sideand a PCI Express memory buffer located on the root co

Figure 9-6: Qsys System for PCI Express with Poor Address Space UtilizationThe following figure uses a filter to hide the Conduit interfaces that are

This design is consuming 1.25 GB of PCIe address space when only 276 MBytes are actually required. Thesolution is to edit the address map to place the

Sp[1:0], that specifies 32-bit or 64-bit PCI Express addressing for the translated address. The mostsignificant bits of the Avalon-MM address are used

Figure 9-10: Avalon-MM-to-PCI Express Address TranslationThe following figure depicts the Avalon-MM-to-PCI Express address translation process. In thi

Figure 9-11: Qsys Design Including Completer Only Single Dword Endpoint for PCI ExpressQsys SystemPCI ExpressRoot ComplexPCIe Linkto HostCPUAvalon-MMI

TX BlockThe TX block sends completion information to the Avalon-MM Hard IP for PCI Express which sends thisinformation to the root complex. The TX com

According to the PCI Express Base Specification, if MSI_enable=0 and the Disable Legacy Interruptbit=1 in the Configuration Space Command register (0x

Transceiver PHY IP Reconfiguration102014.12.15UG-01097_avmmSubscribeSend FeedbackAs silicon progresses towards smaller process nodes, circuit performa

As this figure illustrates, the reconfig_to_xcvr[ <n> 70-1:0] and reconfig_from_xcvr[ <n> 46-1:0]buses connect the two components. You mus

Figure 10-3: Specifying the Number of Transceiver Interfaces for Arria V GZ and Stratix V DevicesThe Transceiver Reconfiguration Controller includes a

Refer to Creating a System with Qsys in volume 1 of the Quartus II Handbook for more information abouthow to use Qsys. For an explanation of each Qsys

Transceiver Reconfiguration Controller Connectivity for Designs UsingCvPIf your design meets the following criteria:• It enables CvP• It includes an a

Throughput Optimization112014.12.15UG-01097_avmmSubscribeSend FeedbackThe PCI Express Base Specification defines a flow control mechanism to ensure ef

Figure 11-1: Flow Control Update LoopCreditsConsumedCounterCreditLimitData PacketFlowControlGatingLogic(CreditCheck)AllowIncrRxBufferData PacketCredit

counter. Essentially, this means the data sink knows the data source has less than a fullMAX_PAYLOAD worth of credits, and therefore is starving.b. Wh

Nevertheless, maintaining maximum throughput of completion data packets is important. Endpointsmust offer an infinite number of completion credits. En

Design Implementation122014.12.15UG-01097_avmmSubscribeSend FeedbackCompleting your design includes additional steps to specify analog properties, pin

a. Double-click in the Assignment Name column and scroll to the bottom of the availableassignments.b. Select VCCA_GXB Voltage.c. In the Value column,

Related InformationReset Sequence for Hard IP for PCI Express IP Core and Application Layer on page 6-3SDC Timing ConstraintsNote: You may need to cha

SDC Constraints for the Qsys Example DesignThe .sdc file includes constraints for the Transceiver Reconfiguration Controller IP Core which isincluded

Optional Features132014.12.15UG-01097_avmmSubscribeSend FeedbackConfiguration via Protocol (CvP)The Hard IP for PCI Express architecture has an option

The driver performs the following transactions with status of the transactions displayed in the ModelSimsimulation message window:1. Various configura

CvP has the following advantages:• Provides a simpler software model for configuration. A smart host can use the PCIe protocol and theapplication topo

Table 13-2: ECRC Operation on RX PathECRC Forwarding ECRC Check Enable(5)ECRC Status Error TLP Forward to Application LayerNoNonone No Forwardedgood N

Table 13-3: ECRC Generation and Forwarding on TX PathAll unspecified cases are unsupported and the behavior of the Hard IP is unknown.ECRC Forwarding

Debugging142014.12.15UG-01097_avmmSubscribeSend FeedbackAs you bring up your PCI Express system, you may face a number of issues related to FPGA confi

packets can be transmitted. If you encounter link training issues, viewing the actual data in hardwareshould help you determine the root cause. You ca

Possible Causes Symptoms and Root Causes Workarounds and SolutionsLink fails withLTSSM stuck inDetect.Active state(1)This behavior may be caused bya P

Possible Causes Symptoms and Root Causes Workarounds and SolutionsLink fails due tounstable rx_signaldetectConfirm that rx_signaldetectbus of the acti

Using the PIPE Interface for Gen1 and Gen2 VariantsRunning the simulation in PIPE mode reduces simulation time and provides greater visibility.Complet

Use Third-Party PCIe AnalyzerA third-party logic analyzer for PCI Express records the traffic on the physical link and decodes traffic,saving you the

Transaction Layer Packet (TLP) Header FormatsA2014.12.15UG-01097_avmmSubscribeSend FeedbackThe following figures show the header format for TLPs witho

# INFO: 36168 ns EP PCI Express Link Control Register (0040): # INFO: 36168 ns Common Clock Config: System Reference Clock Used # INFO: 37960 ns EP PC

Figure A-3: Memory Read Request, 64-Bit AddressingMemory Read Request, 64-Bit Addressing3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5

Figure A-6: I/O Read RequestI/O Read Request3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Figure A-9: Completion Locked without DataCompletion Locked without Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0

Figure A-12: Configuration Write Request Root Port (Type 1)Configuration Write Request Root Port (Type 1)3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5

Figure A-15: Completion Locked with DataCompletion Locked with Data3+2+1+0+7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0Byte 0 0 1

Lane Initialization and ReversalB2014.12.15UG-01097_avmmSubscribeSend FeedbackConnected components that include IP blocks for PCI Express need not sup

Figure B-1: Using Lane Reversal to Solve PCB Routing ProblemsThe following figure illustrates a PCI Express card with ×4 IP Root Port and a ×4 Endpoin

Additional InformationC2014.12.15UG-01097_avmmSubscribeSend FeedbackRevision History for the Avalon-MM InterfaceDate Version Changes Made2014.12.15 14

Date Version Changes Made2014.06.30 14.0Added the following features to the Stratix V Avalon-MM Hard IPfor PCI Express:• Added access to selected Conf

Date Version Changes Made• Enhanced definition of Device ID and Sub-system Vendor ID tosay that these registers are only valid in the Type 0 (Endpoint

Understanding Simulation Log File GenerationStarting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_m

Date Version Changes Made• For Stratix V and Arria V GZ devices, corrected channelplacement diagrams for x8. Both Gen3 Channel Placement Usingthe CMU

Date Version Changes Made2013.05.06 13.0 • Added support for Configuration Space Bypass Mode, allowingyou to design a custom Configuration Space and s

How to Contact AlteraTo locate the most up-to-date information about Altera products, refer to the following table.Contact (1)Contact Method AddressT

Visual Cue Meaningbold type Indicates directory names, project names, disk drivenames, file names, file name extensions, softwareutility names, and GU

Visual Cue Meaningh The question mark directs you to a software helpsystem with related information.f The feet direct you to another document or websi

Generating Quartus II Synthesis Files1. On the Generate menu, select Generate HDL.2. For Create HDL design files for synthesis, select Verilog.You can

Datasheet12014.12.15UG-01097_avmmSubscribeSend FeedbackStratix V Avalon-MM Interface for PCIe DatasheetAltera® Stratix® V FPGAs include a configurable

a. In the <project_dir>/ep_g2x4_avmm128/synth/, open ep_g2x4_avmm128.v.b. Comment out the declaration for pcie_a10_hip_0_hip_ctrl_test_in.c. Add

Parameter Settings32014.12.15UG-01097_avmmSubscribeSend FeedbackStratix V and Arria V GZ Avalon-MM System SettingsTable 3-1: System Settings for PCI E

Parameter Value Descriptionof flow control credits. You can set the Maximum payloadsize parameter on the Device tab.The Message window dynamically upd

Parameter Value DescriptionUse 62.5 MHzapplication clockOn/Off This mode is only available only for Gen1 ×1.Enable configu‐ration via PCIExpress (CvP)

Parameter Value DescriptionSizeNot configurableSpecifies the memory size calculated from otherparameters you enter.Device Identification RegistersTabl

Related InformationPCI Express Base Specification 2.1 or 3.0PCI Express and PCI Capabilities ParametersThis group of parameters defines various capabi

Parameter Possible Values Default Value Description• 0111 Ranges A, B, and C• 1110 Ranges B, C and D• 1111 Ranges A, B, C, and DAll other values are r

Parameter Value Default Value DescriptionEnableECRCforwardingon theAvalon-STinterfaceOn/Off Off When On, enables ECRC forwarding to the ApplicationLay

MSI and MSI-X CapabilitiesTable 3-7: MSI and MSI-X Capabilities Parameter Value DescriptionMSI messagesrequested1, 2, 4, 8, 16 Specifies the number of

Power ManagementTable 3-8: Power Management ParametersParameter Value DescriptionEndpoint L0sacceptablelatencyMaximum of 64 nsMaximum of 128 nsMaximum

Link Width in Gigabits Per Second (Gbps)x1 x2 x4 x8PCI Express Gen2(5.0 Gbps)4 8 16 32PCI Express Gen3(8.0 Gbps)7.87 15.75 31.51 63Refer to the PCI Ex

Avalon Memory‑Mapped System SettingsTable 3-9: Avalon Memory-Mapped System SettingsParameter Value DescriptionAvalon-MM data width64-bit128-bitSpecifi

Parameter Value DescriptionSingle DW Completer On/OffThis is a non-pipelined version of Completer Onlymode. At any time, only a single request can beo

Parameter Value DescriptionEnable hard IP status bus On/Off When you turn this option on, your top-level variantincludes the signals necessary to conn

Related InformationClock Domains on page 6-5UG-01097_avmm2014.12.15Avalon Memory‑Mapped System Settings3-13Parameter SettingsAltera CorporationSend Fe

64- or 128-Bit Avalon-MM Interface to theApplication Layer42014.12.15UG-01097_avmmSubscribeSend FeedbackThis chapter describes the top-level signals o

Figure 4-1: 64- or 128-Bit Avalon-MM Interface to the Application Layertx_out0[<n>:0]rx_in0[<n>:0]1-Bit Serialcra_readdata[31:0]cra_waitre

32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) SlaveSignalsThe optional CRA port for the full-featured IP core allows upstream PCI Expres

Table 4-2: Avalon-MM RX Master Interface SignalsSignals that include Bar number 0 also exist for BAR1–BAR5 when additional BARs are enabled.Signal Nam

Figure 4-2: Simultaneous DMA Read, DMA Write, and Target AccessRxmRead_oRxmReadDataValid_iRxmReadData_i[63:0]RxmResetRequest_oRxmAddress_o[31:0]RxmWai

Table 4-3: Avalon-MM TX Slave Interface SignalsSignal Name Direction DescriptionTxsChipSelect_iInput The system interconnect fabric asserts this signa

Table 1-2: Feature Comparison for all Hard IP for PCI Express IP CoresThe table compares the features of the four Hard IP for PCI Express IP Cores.Fea

Signal Name Direction DescriptionTxsByteEnable_i[<w>-1:0]Input Write byte enable for data. A burst must be continuous.Therefore all intermediate

Clock SignalsTable 4-4: Clock SignalsSignal Direction DescriptionrefclkInput Reference clock for the IP core. It must have the frequencyspecified unde

Table 4-5: Reset SignalsSignal Direction DescriptionnporInput Active low reset signal. In the Altera hardware example designs,npor is the OR of pin_pe

Signal Direction Descriptioneven if the VVCCPGM of the bank is not 3.3V if the following 2conditions are met:• The input signal meets the VIH and VIL

Signal Direction Descriptionderr_cor_ext_rpl Output Indicates a corrected ECC error in the retry buffer. This signal isfor debug only. Because the err

Signal Direction Descriptionko_cpl_spc_header[7:0]Output The Application Layer can use this signal to build circuitry toprevent RX buffer overflow for

Signal Direction Description• 10011: Loopback.Exit• 10100: Hot.Reset• 10101: L0s• 11001: L2.transmit.Wake• 11010: Speed.Recovery• 11011: Recovery.Equa

Interrupts for Endpoints when Multiple MSI/MSI‑X Support Is EnabledTable 4-7: Exported Interrupt Signals for Endpoints when Multiple MSI/MSI‑X Support

Signal Direction DescriptionIntxAck_oOutput This signal is the acknowledge for IntxReq_i. It is asserted for atleast one cycle either when either of t

Table 4-8: Transceiver Control SignalsIn this table, <n> is the number of interfaces required.Signal Name Direction Descriptionreconfig_from_xcv

Feature Avalon‑ST Interface Avalon‑MMInterfaceAvalon‑MM DMA Avalon‑ST Interface with SR-IOVTransactionLayer Packettype (TLP) • Memory ReadRequest• Mem

Hard IP Status ExtensionTable 4-10: Hard IP Status Extension SignalsThis optional bus adds signals that are useful for debugging to the top-level vari

Signal Direction Descriptionrx_st_bar[7:0]Output The decoded BAR bits for the TLP. Valid for MRd, MWr, IOWR, andIORD TLPs. Ignored for the completion

Signal Direction Descriptionrx_st_sopOutput Indicates that this is the first cycle of the TLP when rx_st_validis asserted.rx_st_valid Output Clocks r

Table 4-11: Mapping Between tl_cfg_sts and Configuration Space Registerstl_cfg_sts Configuration Space Register Description[52:49] Device Status Regis

tl_cfg_sts Configuration Space Register Description[29:25] Status Register[15:11] Records the following 5 primary commandstatus errors:• Bit 15: detec

Figure 4-6: Multiplexed Configuration Register Information Available on tl_cfg_ctlFields in blue are available only for Root Ports.01cfg_dev_ctrl[15:0

Register Width Direction Descriptioncfg_link_ctrl16 Output cfg_link_ctrl[15:0]is the primary Link Controlof the PCI Express capability structure.For G

Register Width Direction Descriptioncfg_msi_addr64 Output cfg_msi_add[63:32] is the message signaledinterrupt (MSI) upper message address. cfg_msi_add

Register Width Direction Descriptioncfg_tcvcmap24 Output Configuration traffic class (TC)/virtual channel(VC) mapping. The Application Layer uses this

Bit(s) Field Description[6:4] multiple messageenableThis field indicates permitted values for MSI signals. For example,if “100” is written to this fie

Feature Avalon‑ST Interface Avalon‑MMInterfaceAvalon‑MM DMA Avalon‑ST Interface with SR-IOVOut-of-ordercompletions(transparent tothe ApplicationLayer)

Serial Data SignalsTable 4-14: 1-Bit Interface SignalsSignal Direction Descriptiontx_out[7:0](1)Output Transmit output. These signals are the serial o

Figure 4-9: Stratix V GX/GT/GS Devices with Four PCIe Hard IP Blocks3 Ch6 Ch6 Ch6 Ch6 Ch6 Ch3 Ch6 Ch6 Ch6 Ch6 Ch6 ChPCIeHardIPPCIeHardIPPCIeHardIPIOBA

Channel Placement in Arria V GZ and Stratix V GX/GT/GS DevicesFigure 4-10: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the

Figure 4-11: Arria V GZ and Stratix V GX/GT/GS Gen3 Channel Placement Using the CMU and ATX PLLsGen3 requires two PLLs to facilitate rate switching be

Figure 4-12: Arria V GZ and Stratix V GX/GT/GS Gen1 and Gen2 Channel Placement Using the ATX PLLSelecting the ATX PLL has the following advantages ove

Table 4-15: PIPE Interface SignalsSignal Direction Descriptiontxdata0[7:0]Output Transmit data <n>. This bus transmits data on lane <n>.tx

Signal Direction Descriptionpowerdown0[1:0] Output Power down <n>. This signal requests the PHY to change itspower state to the specified state

Signal Direction Descriptionsim_pipe_rate[1:0]Output The 2-bit encodings have the following meanings:• 2’b00: Gen1 rate (2.5 Gbps)• 2’b01: Gen2 rate (

Signal Direction Description• 5’b11010: Speed.Recovery• 5’b11011: Recovery.Equalization, Phase 0• 5’b11100: Recovery.Equalization, Phase 1• 5’b11101:

Test SignalsTable 4-16: Test Interface SignalsThe test_in bus provides run-time control and monitoring of the internal state of the IP core.Signal Dir

• V-Series Avalon-MM DMA Interface for PCIe Solutions User GuideRelease InformationTable 1-3: Hard IP for PCI Express Release InformationItem Descript

Registers52014.12.15UG-01097_avmmSubscribeSend FeedbackCorrespondence between Configuration Space Registers and the PCIeSpecificationTable 5-1: Corres

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x170:0x17C Reserved N/A0x180:0x1FC Virtual channel arbit

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x018 Base Address 2Secondary Latency Timer, Subordinate

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x068 MSI-X Message Control Next Cap PtrCapability IDMSI

Type 0 Configuration Space RegistersFigure 5-1: Type 0 Configuration Space Registers - Byte Address Offsets and LayoutEndpoints store configuration da

Type 1 Configuration Space RegistersFigure 5-2: Type 1 Configuration Space Registers (Root Ports)0x00000x004Device ID31242316158700x0080x00C0x0100x014

Figure 5-4: MSI-X Capability Structure0x0680x06C0x070Message Control Next Cap PtrMSI-X Table OffsetMSI-X Pending Bit Array (PBA) Offset31 24 23 16 15

Figure 5-7: PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, reg

Altera-Defined VSEC RegistersFigure 5-8: VSEC RegistersThis extended capability structure supports Configuration via Protocol (CvP) programming and de

Table 5-3: Altera‑Defined Vendor Specific HeaderYou can specify these values when you instantiate the Hard IP. These registers are read-only at run-ti

ConfigurationsThe Avalon-MM Stratix V Hard IP for PCI Express includes a full hard IP implementation of the PCIExpress stack comprising the following

Table 5-7: CvP StatusThe CvP Status register allows software to monitor the CvP status signals.Bits Register Description Reset Value Access[31:26] Res

Bits Register Description Reset Value Access[1] HIP_CLK_SEL. Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The follo

Bits Register Description Reset Value Access[1] START_XFER. Sets the CvP output to the FPGA control blockindicating the start of a transfer.1’b0 RW[0]

The following table describes the four subregions.Table 5-11: Avalon-MM Control and Status Register Address SpacesAddressRange Address Space Usage0x00

Address Range Register0x3070 INT-X Interrupt Enable Register for Root Ports0x3070 INT-X Interrupt Enable Register for Endpoints0x3A00-0x3A1F Avalon-MM

Bit Name Access Description[15:0] AVL_IRQ_ASSERTED[15:0] RO Current value of the Avalon-MM interrupt(IRQ) input ports to the Avalon-MM RXmaster port:•

Bits Name Access Description[15:0]AVL_IRQ_VectorRO Stores the interrupt vector of the systeminterconnect fabric. The host softwareshould read this reg

Address Name Access Description0x0904 A2P_MAILBOX1 RO Avalon-MM-to-PCI Express Mailbox 10x0908 A2P_MAILBOX2 RO Avalon-MM-to-PCI Express Mailbox 20x090

Address Bits Name Access Description0x1008[1:0]A2P_ADDR_SPACE1RW Address space indication for entry 1. Refer to thefollowing encodings are defined:• 2

Bits Name Access Description1ERR_PCI_READ_FAILURERW1C When set to 1, indicates the failure of aPCI Express read. This bit can also becleared by writin

PCIe LinkPCIe Hard IPRPSwitchPCIeHard IPRPUser ApplicationLogicPCIe Hard IPEPPCIe LinkPCIe LinkUser ApplicationLogicAltera FPGA Hard IP for PCI Expres

Table 5-20: INT‑X Interrupt Enable Register for Endpoints, 0x3070Bits Name Access Description[31:0]PCI Express to Avalon-MMInterrupt EnableRW When set

The PCI Express-to-Avalon-MM Mailbox registers are read-only at the addresses shown in thefollowing table. The Avalon-MM processor reads these registe

Byte OffsetRegister Dir Description14'h3C08 cfg_link_ctrl[15:0]O cfg_link_ctrl[15:0]is the primary Link Controlof the PCI Express capability stru

Byte OffsetRegister Dir Description14'h3C28 cfg_msi_addr_hi[63:32]O cfg_msi_add[63:32] is the MSI upper messageaddress.14'h3C2C cfg_io_bas[1

Byte OffsetRegister Dir Description14'h3C58 cfg_tcvcmap[23:0]O Configuration traffic class (TC)/virtual channel(VC) mapping. The Application Laye

Byte OffsetRegister Dir Description• 10011: Loopback.Exit• 10100: Hot.Reset• 10101: LOs• 11001: L2.transmit.Wake• 11010: Speed.Recovery• 11011: Recove

Figure 5-10: Layout of Data with 3 Dword HeadersHeader 1 [63:32]Cycle 1Register 1Register 0Register 1Register 0Register 1Register 0Register 1Register

The TX TLP programming model scales with the data width. The Application Layer performs the samewrites for both the 64- and 128-bit interfaces. The Ap

Table 5-24: Avalon‑MM Interrupt Status Registers for Root Ports, 0x3060Bits Name AccessModeDescription[31:5] Reserved — —[4]RPRX_CPL_RECEIVEDRW1C Set

Bit Name AccessModeDescription[2]INTC_RECEIVED_ENARW When set to 1’b1, enables the assertionof CraIrq_o when the Root PortInterrupt Status register IN