Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual Page 22
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Parameter Value Description
of flow control credits. You can set the Maximum payload
size parameter on the Device tab.
The Message window dynamically updates the number of
credits for Posted, Non-Posted Headers and Data, and
Completion Headers and Data as you change this selection.
• Minimum—configures the minimum PCIe specification
allowed for non-posted and posted request credits, leaving
most of the RX Buffer space for received completion
header and data. Select this option for variations where
application logic generates many read requests and only
infrequently receives single requests from the PCIe link.
• Low—configures a slightly larger amount of RX Buffer
space for non-posted and posted request credits, but still
dedicates most of the space for received completion header
and data. Select this option for variations where application
logic generates many read requests and infrequently
receives small bursts of requests from the PCIe link. This
option is recommended for typical endpoint applications
where most of the PCIe traffic is generated by a DMA
engine that is located in the endpoint application layer
logic.
• Balanced—configures approximately half the RX Buffer
space to received requests and the other half of the RX
Buffer space to received completions. Select this option for
variations where the received requests and received
completions are roughly equal.
Reference clock
frequency
100 MHz
125 MHz
The PCI Express Base Specification 3.0 requires a
100 MHz ±300 ppm reference clock. The 125 MHz reference
clock is provided as a convenience for systems that include a
125 MHz clock source. For more information about Gen3
operation, refer to 4.3.8 Refclk Specifications for 8.0 GT/sin the
specification.
For Gen3, Altera recommends using a common reference
clock (0 ppm) because when using separate reference clocks
(non 0 ppm), the PCS occasionally must insert SKP symbols,
potentially causes the PCIe link to go to recovery. Stratix V
PCIe Hard IP in Gen1 or Gen2 modes are not affected by this
issue. Systems using the common reference clock (0 ppm) are
not affected by this issue. The primary repercussion of this is a
slight decrease in bandwidth. On Gen3 x8 systems, this
bandwidth impact is negligible. If non 0 ppm mode is
required, so that separate reference clocks are being used,
please contact Altera for further information and guidance.
3-2
Stratix V and Arria V GZ Avalon-MM System Settings
UG-01097_avmm
2014.12.15
Altera Corporation
Parameter Settings
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
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