Altera Stratix V Avalon-MM Interface for PCIe Solutions User Manual Page 15
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Refer to Creating a System with Qsys in volume 1 of the Quartus II Handbook for more information about
how to use Qsys. For an explanation of each Qsys menu item, refer to About Qsys in Quartus II Help.
Related Information
• Creating a System with Qsys
• About Qsys
Generating the Example Design
1. On the Generate menu, select Generate Testbench System. The Generation dialog box appears.
2. Under Testbench System, set the following options:
a. For Create testbench Qsys system, select Standard, BFMs for standard Qsys interfaces.
b. For Create testbench simulation model, select Verilog.
3. You can retain the default values for all other parameters.
4. Click Generate.
5. After Qsys reports Generation Completed, click Close.
6. On the File menu, click Save.
The following table lists the testbench and simulation directories Qsys generates.
Table 2-1: Qsys System Generated Directories
Directory Location
Qsys system
<project_dir>/ep_g2x4
Testbench
<project_dir>/ep_g2x4/testbench/<cad_vendor>
Simulation Model
<project_dir>/ep_g2x4/testbench/ep_g2x4_tb/
simulation/
The design example simulation includes the following components and software:
• The Qsys system
• A testbench. You can view this testbench in Qsys by opening <project_dir>/ep_g2x4/testbench/ep_g2x4_
tb.qsys.
• The ModelSim software
Note:
You can also use any other supported third-party simulator to simulate your design.
Complete the following steps to run the Qsys testbench:
1. In a terminal window, change to the <project_dir>/ep_g2x4/testbench/mentor directory.
2. Start the ModelSim
®
simulator.
3. Type the following commands in a terminal window:
a. do msim_setup.tcl
b. ld_debug
c. run 140000 ns
UG-01097_avmm
2014.12.15
Generating the Example Design
2-3
Getting Started with the Avalon‑MM Stratix V Hard IP for PCI Express
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
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