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Hardware Library
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2014.12.15
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The Altera SoC FPGA Hardware Library (HWLIB) was created to address the needs of low-level software
programmers who require full access to the configuration and control facilities of SoC FPGA hardware.
An additional purpose of the HWLIB is to mitigate the complexities of managing the operation of a
sophisticated, multi-core application processor and its integration with hardened IP peripheral blocks and
programmable logic in a SoC architecture.
Figure 8-1: HW Library
Within the context of the SoC HW/SW ecosystem, the HWLIB is capable of supporting software develop‐
ment in conjunction with full featured operating systems or standalone bare-metal programming
environments. The relationship of the HWLIB within a complete SoC HW/SW environment is illustrated
in the above figure.
The HWLIB provides a symbolic register abstraction layer known as the SoC Abstraction Layer (SoCAL)
that enables direct access and control of HPS device registers within the address space. This layer is
necessary for enabling several key stakeholders (boot loader developers, driver developers, board support
package developers, debug agent developers, and board bring-up engineers) requiring a precise degree of
access and control of the hardware resources.
The HWLIB also deploys a set of Hardware Manager (HW Manager) APIs that provides more complex
functionality and drivers for higher level use case scenarios.
The HWLIB has been developed as a source code distribution. The intent of this model is to provide a
useful set of out-of-the-box functionality and to serve as a source code reference implementation that a
user can tailor accordingly to meet their target system requirements.
The capabilities of the HWLIB are expected to evolve and expand over time particularly as common use
case patterns become apparent from practical application in actual systems.
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Overview 6
- Device Tree Binary 7
- Related Information 10
- Installation Folders 11
- Installing the SoC EDS 11
- Licensing 13
- Activating the License 14
- 5. Click Next 17
- Jumper Settings 21
- Start Eclipse 25
- Create New Project 25
- Set the Linker Script 28
- Write Application Source Code 31
- Build Application 34
- TestProject.axf executable 35
- Debug Application 36
- Create a New Project 45
- Figure 4-6: New Project 46
- Create a Linker Script 48
- Figure 4-14: Settings 55
- Figure 4-16: New Source File 57
- Figure 4-17: New Source File 58
- Figure 4-19: Build Project 60
- Starting the Eclipse IDE 71
- Application Console 76
- Sequence Sample Application 85
- Function 85
- Used Hardware 85
- Libraries APIs 85
- Description 85
- Debugging the Kernel 92
- Configuring Linux 97
- File Name Description 100
- Altera Corporation 101
- Getting Started Guides 101
- Send Feedback 101
- Figure 4-59: Browse Target 105
- 2014.12.15 108
- Getting Started with Tracing 111
- Figure 4-67: Trace Into ETF 112
- FPGA Triggering HPS Example 119
- HPS Triggering FPGA Example 123
- ARM DS-5 Altera Edition 126
- Bare-metal Project Management 127
- Creating Project 130
- Build Settings 134
- Build > Settings 135
- Creating a Project 136
- Figure 5-10: New Project 137
- Baremetal GCC. Click Finish 138
- Linker Script 140
- + Build > Settings 146
- Debugging 147
- Debug Configuration Options 150
- Connection Options 151
- Files Options 156
- Debugger Options 156
- RTOS Awareness 157
- Arguments 158
- Environment 158
- DTSL Options 159
- Cross Trigger Settings 160
- Trace Buffer Settings 161
- Cortex-A9 Settings 162
- STM Settings 163
- ETR Settings 163
- ETF Settings 164
- Embedded Command Shell 165
- HPS Preloader User Guide 166
- Hardware Handoff Files 168
- Using .tcl Scripts 169
- Option Required Description 171
- BSP Settings 174
- 2013.05.03 175
- Reset Assert Settings 179
- Preloader Compilation 180
- Preloader Image Tool 181
- Tool Usage 183
- Output Image Layout 184
- Hardware Library 188
- Feature Description 189
- Subscribe 191
- HPS Flash Programmer 192
- Option Short 193
- Required Description 193
- Supported Memory Devices 196
- Bare-Metal Compiler 198
- SD Card Boot Utility 199
- Tool Options 200
- Linux Compiler 202
- Device Tree Generator 205
- Yocto Plugin 206
- Support and Feedback 207
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