Altera SoC Embedded Design Suite User Manual Page 1

Altera SoC Embedded Design Suite UserGuideSubscribeSend Feedbackug-11372014.12.15101 Innovation DriveSan Jose, CA 95134www.altera.com

Hardware – Software Development FlowThe Altera hardware-to-software handoff utilities allow hardware and software teams to work independ‐ently and fol

Figure 4-54: Select Imported File5. Click Finish. The project is imported. The project files are displayed in the Project Explorer panel.The following

Compiling the Linux Application Debugging Sample Application1. To compile the application, select the project in Project Explorer.2. Select Project &g

Figure 4-56: Create New Connection4. In the first page of the New Connection wizard, named Remote System Type view, select SSH onlyand click Next.ug-1

Figure 4-57: New Connection window5. Enter the IP address of the board in the Host Name field. Click Finish to create the connection.4-84Setting up Re

Figure 4-58: Enter Target IP Address6. In the Remote Systems panel, click the Target IP > Sftp Files > Root. This opens a dialog box to enterthe

Figure 4-59: Browse Target7.Assign root to User ID and assign the password you selected in the Configuring Linux section toPassword. Select the Save U

Figure 4-60: Target Username and Password8. Eclipse asks for confirmation of authenticity of the board. Click Yes.9. Remote System Explorer shows the

Figure 4-61: Target FilesRunning the Linux Application Debugging Sample ApplicationAt this stage, we have a compiled Linux application and a properly

Figure 4-62: Connection Settings6. Go to Files tab, and set the Target Configuration parameters:a. Select the Application on host to download to be th

Figure 4-63: Target Configuration7. Click the Debug button. A dialog window appears asking to switch to Debug perspective. Click Yes.8. Eclipse downlo

Installing the Altera SoC Embedded DesignSuite22014.12.15ug-1137SubscribeSend FeedbackYou must install the Altera SoC Embedded Design Suite (EDS) and

Figure 4-64: Program DownloadedNote: At this stage, all the usual debugging features of DS-5 can be used, such as breakpoints, viewvariables, register

Figure 4-65: Hello MessageGetting Started with TracingARM DS-5 provides powerful tracing features, allowing PTM and STM tracing. It allows different t

Figure 4-66: Edit DTSL Options Button5. In the DTSL windowDTSL dialog box, click Trace Buffer tab and select On Chip Trace Buffer (ETF)for the Trace c

Figure 4-68: Enable PTM Tracing7. In the ETF tab, select the ETF to be enabled; and a buffer size of 0x8000, to match the ETF size on theCyclone V SoC

Figure 4-70: Trace WindowThe tracing window shows:• Core instructions as they were executed• Percentage occupied by each function• Histogram with func

Getting Started with Cross TriggeringThe Altera SoC offers powerful cross-triggering capability between the HPS and the FPGA fabric. TheHPS can trigge

6. In SignalTap II, on the JTAG Chain Configuration > Device, select the FPGA device.Figure 4-72: Select FPGA device7. In SignalTap II, under SOF M

Figure 4-75: Signal Tap Ready to AcquireRelated InformationGetting Started with Running Linux on page 4-2For more information, refer to the Getting St

Figure 4-76: Debug Configuration - Connection2. The Cross-Trigger tab of the DTSL Configuration Editor allows Cross-trigger configuration.Figure 4-77:

In order to allow HPS cross triggers to trigger FPGA, you need to:• Check the Enable HPS > FPGA Cross Triggering check box• Check the Assume Cross

5. Select All the components to be installed, and click Next. The installer displays a summary of theinstallation.6. Click Next to start the installat

Figure 4-79: Enable Trigger Out to HPS6. In Signal Tap II, configure the Trigger in to be disabled by setting its pattern to Don't Care. In thiss

9. SignalTap II will run the analysis and wait for the trigger from the DIP switch:Figure 4-82: Acquisition in Progress10.Change the state of the FPGA

Enabling Cross-triggering on FPGAFor this getting started scenario, we are using Quartus SignalTap II utility to control FPGA cross-triggering.Figure

Quartus SignalTap II GUI has the above depicted Trigger panel that controls cross-triggering:• The Trigger In panel determines whether HPS can trigger

Figure 4-86: Trigger Signals Disabled5. In Signal Tap II, configure the Trigger in to be sensitive to both edges, so that the SignalTap II sendsthe tr

Figure 4-88: Run Analysis8. SignalTap II will run the analysis and wait for the trigger from HPS:Figure 4-89: Acquisition in Progress9. In Eclipse deb

ARM DS-5 Altera Edition52014.12.15ug-1137SubscribeSend FeedbackThe ARM DS-5 AE is based on the ARM Development Studio 5 (DS-5) Toolkit and is a device

The advantage of starting Eclipse from the Embedded Command Shell is that all the utilities are added tothe search path, and they can be used directly

Figure 5-1: Creating a Project with Existing Code3. Type the folder name in the Existing Code Location edit box and then click Finish.ug-11372014.12.1

Figure 5-2: Import Existing Code window4. Create a Makefile in that folder, and define the rules required for compiling the code. Make sure it hasthe

Licensing32014.12.15ug-1137SubscribeSend FeedbackThe SoC EDS is available with three different licensing options:• Subscription edition• Free web edit

Figure 5-3: Eclipse IDE - build process invoked6. If the compilation tools issue errors, Eclipse parses and formats them for you.GCC-Based Bare-Metal

Figure 5-4: Create a New Project2. Select C/C++ > C Project and click Next.5-6Creating Projectug-11372014.12.15Altera CorporationARM DS-5 Altera Ed

Figure 5-5: New C Project Created3. Determine if you want to create a Bare-metal executable empty project or a Bare-metal library emptyproject.a. Bare

Figure 5-6: Bare-metal Executable Project Typeb. Bare-metal librarySelect Bare-metal Library > Empty Project and click Finish.5-8Creating Projectug

Figure 5-7: Bare-metal Library Project TypeBuild SettingsOnce the project is created, the project properties can be accessed by going to Project >

Figure 5-8: Project PropertiesThen, in the Project Properites window, the Compilation settings can be accessed by selecting C/C++Build > Settings5-

Figure 5-9: Project SettingsThe Build Settings incldue detailed settings for all tools:• Compiler• Assembler• LinkerThe Getting Started Guides chapter

Figure 5-10: New Project3. Select C/C++ > C Project and click Next.5-12Creating a Projectug-11372014.12.15Altera CorporationARM DS-5 Altera Edition

Figure 5-11: Create a New C Project4. Continue with one of the following options:1. Select "Project Type" as Executable > Empty Project a

Figure 5-12: Create an Empty Project with a Toolchain Selected2. Select Static Library > Empty Project and click Finish.5-14Creating a Projectug-11

the Altera website (http://dl.altera.com/soceds) and then activate your license in DS-5, as shown in theActivating the License section.Related Informa

Figure 5-13: Create an Empty Project Without a ToolchainLinker ScriptARM DS-5 AE offers a visual tool to help create linker scripts.1. Go to File >

Figure 5-14: Creating a Linker Script2. Select Scatter File Editor > Scatter File and press Next.5-16Linker Scriptug-11372014.12.15Altera Corporati

Figure 5-15: Creating a Scatter File3. Select the location of the new file, type in the file name and press Finish.ug-11372014.12.15Linker Script5-17A

Figure 5-16: Create a New Scatter File Resource4. The linker script file can be edited directly as shown in the example below.5-18Linker Scriptug-1137

Figure 5-17: Linker Script Example5. The file can also be edited by using the tools on the Outline view for the file.ug-11372014.12.15Linker Script5-1

Figure 5-18: Editing "Scatter.scat" File Using Tools on the Outline ViewBuild Settings1. Once the project is created, the project properties

Figure 5-19: Project Properties2. Then, in the Project Properties window, the "Compilation" settings can be accessed by selecting C/C++ Buil

Figure 5-20: Project SettingsThe build settings include detailed settings for all tools:• Compiler• Assembler• LinkerThe "Getting Started with AR

The settings for a debugging session are stored in a Debug Configuration. The Debug Configurationswindow is accessible from the Run > Debug Configu

Figure 5-22: Create New Debug ConfigurationThe Eclipse IDE will assign a default name to the configuration, which can then be edited by you.5-24Creati

Figure 3-2: Accessing ARM License Manager3. The License Manager - View and edit licenses dialog box opens and shows that a license is notavailable. Cl

Figure 5-23: Rename Debug ConfigurationDebug Configuration OptionsThis section lists the Debug Configuration options, which allows you to specify the

Connection OptionsThe Connection tab allows the user to select the desired target. The following targets are available for theAltera platforms:Arria V

• Bare Metal Debug• Debug HPS0 Cortex-A9_0• Debug HPS0 Cortex-A9_1• Debug HPS0 Cortex-A9x2_SMP• Debug HPS1 Cortex-A9_0• Debug HPS1 Cortex-A9_1• Debug

• Application Debug• Connections via gdbserver• Connect to already running gdbserver• Download and debug application• Start dbgserver and debug target

For the Linux Application Debug targets, the connection parameters will be different depending onwhich type of connection was selected. The following

Figure 5-26: Linux Application Debugging – Download And Debug ApplicationNote: For the Linux Application Debug, the Connection needs to be configured

Files OptionsThe Files tab allows the following settings to be configured:• Application on host to download – the file name of the application to be d

Figure 5-28: Debugger SettingsRTOS AwarenessThe RTOS Awareness tab allows the user to enable Keil CMSIS-RTOS RTX awareness for the debuggerin case tha

Figure 5-29: RTOS Awareness SettingsRelated InformationKeil WebsiteFor more information about RTOS Awareness, refer to the Embedded Development Tools

Figure 5-31: Environment SettingsDTSL OptionsThe Debug and Trace Services Layer (DTSL) provides tracing features. To configure trace options, in yourp

Figure 3-3: ARM License Manager4. In the Add License - Obtain a new licenses dialog box, select the type of license to enter. In thisexample, select t

Figure 5-32: Debug Configurations - DTSL Options - EditCross Trigger SettingsThe Cross Trigger tab allows the configuration of the cross triggering op

Figure 5-33: DTSL Configuration Editor - Cross TriggerTrace Buffer SettingsThe Trace Buffer tab allows the selection of the destination of the trace i

Figure 5-35: DTSL Configuration Editor - Trace Buffer > Timestamp FrequencyCortex-A9 SettingsThe Cortex-A9 tab allows the selection of the desired

• Cycle Accurate – check to create cycle accurate tracing• Trace capture range – check to enable tracing only a certain address interval• Start Addres

ETF SettingsThe ETF tab allows the configuration of the Embedded Trace FIFO(ETF) settings.The Embedded Trace FIFO is a 32KB buffer residing on HPS tha

Embedded Command Shell62014.12.15ug-1137SubscribeSend FeedbackThe purpose of the embedded command shell is to provide an option for you to invoke the

HPS Preloader User Guide72013.05.03ug-1137SubscribeSend FeedbackThere are four stages of the hard processor system (HPS) booting process; the preloade

1. Configures the HPS pins I/O configuration shift register (IOCSR) and pin multiplexing2. Configures the HPS phase-locked loops (PLLs) and clocking3.

Figure 7-2: Preloader Support Package Generator FlowQsysQuartusHardwareHandoff FilesGeneratePreloaderSupportPackageGeneratorUser Inputs(Qsys Settings,

• On a Windows-based system, run the batch file<SoC EDS installation directory>\Embedded_Command_Shell.bat• On a Linux-based system, run the she

Figure 3-4: Add License - Obtain a New License5. Click Next.6. In the Add License - Choose Host ID dialog box, select the Host ID (Network Adapter MAC

Figure 7-3: PSP Directorysettings.bspMakefilegeneratedbsp_directoryThe BSP files include:• settings.bsp – the settings file containing all BSP setting

Table 7-1: User Parameters: bsp-create-settingsOption Required Description--type <bsp-type> YesThis option specifies the type of BSP."spl&q

Table 7-2: User Parameters: bsp-update-settingsOption Required Description--settings <settings-file> YesThis option specifies the path to an exi

Option Required Description--get-all NoThis option shows all the BSP settings values.When using --get-all,you must also use --show-names.--show-names

Table 7-4: User Parameters: bsp-generate-filesOption Required Description--settings <settings-file> YesThis option specifies the path to an exis

BSP Setting Type Default Value Descriptionspl.CROSS_COMPILE Stringarm-altera-eabiThis setting specifies the crosscompilation tool chain for use.spl.bo

BSP Setting Type Default Value Descriptionspl.boot.FAT_BOOT_PARTITION Decimal 1When FAT partition support isenabled, this specifies the FATpartition w

BSP Setting Type Default Value Descriptionspl.boot.WARMRST_SKIP_CFGIO Boolean TrueThis setting enables thepreloader to skip IOCSR and pinmultiplexing

BSP Setting Type Default Value Descriptionspl.debug.HARDWARE_DIAGNOSTIC Boolean FalseThis setting enables hardwarediagnostic support, enablinghardware

BSP Setting Type Default Value Descriptionspl.warm_reset_handshake.SDRAM Boolean True This setting enables the resetmanager to request that theSDRAM c

Figure 3-5: Add License - Choose host ID7. In the Add License - Developer account details dialog box, enter an ARM developer (Silver) account.If you d

BSP Setting Default Valuespl.reset_assert.GPIO1 Falsespl.reset_assert.GPIO2 Falsespl.reset_assert.L4WD1 Falsespl.reset_assert.OSC1TIMER1 Falsespl.rese

Note: The options for generating the RBF file need to match the MSEL settings on the board.RBF File Stored in QSPI Flash MemoryThe following steps are

The preloader image tool makes the following assumptions:1. The input file format is raw binary. You must use the objcopy utility provided with the GN

Figure 7-5: Header FormatSimple ChecksumProgram LengthReserved (0x0)Flags VersionValidation Word (0x31305341)0x480x440x40Tool UsageThe preloader image

Output Image LayoutBase AddressYou must place the preloader image at 0x0 for NAND and QSPI flash. The SD/MMC flash has a MBR thatpoints to a specific

Serial NOR FlashEach QSPI boot image occupies an integer number of sectors unless subsector erase is supported; thisensures that updating one image do

The preloader reads the following information from mkimage header:1. Image magic number - determines if the image is a valid boot image2. Image data s

Example 7-8: Creating a Bare-metal Application Imagemkimage -A arm -O u-boot -T standalone -C none -a 0x02100000 -e 0 -n "baremetal image" -

Hardware Library82014.12.15ug-1137SubscribeSend FeedbackThe Altera SoC FPGA Hardware Library (HWLIB) was created to address the needs of low-level sof

In general, the HWLIB assumes to be part of the system software that is executing on the Hard ProcessorSystem (HPS) in privileged supervisor mode and

address and generate the license directly from the ARM Self-Service web page on the ARMwebsite (silver.arm.com), then select the "Already have a

implemented by the compound application of other functions in the HW Manager API to build morecomplex operations (for example, software controlled con

HPS Flash Programmer User Guide92014.12.15ug-1137SubscribeSend FeedbackThe Altera Quartus II software and Quartus II Programmer include the HPS flash

The target portion is the HPS in the SoC. The target accepts the programming data flash content andrequired information about the target flash memory

Table 9-1: HPS Flash Programmer ParametersOption ShortOptionRequired Description--cable -cYes This option specifies what download cable touse.To obtai

Option ShortOptionRequired Description--operation -oYes This option specifies the operation to beperformed. The following operations aresupported:• I:

Example 9-1: Program File to Address 0 of Flashquartus_hps –c 1 –o P input.bin programs the input file (input.bin) into the flash, startingat flash ad

Supported Memory DevicesTable 9-2: QSPI FlashManufacturer Device ID DIE # Density (Mb)Micron 0x18BA20 1 128Micron 0x19BA20 1 256Micron 0x20BA20 2 512M

Note: Starting with version 14.1, the HPS Flash Programmer supports all ONFI compliant NAND flashdevices that are supported by the HPS QSPI Flash Cont

Bare-Metal Compiler102014.12.15ug-1137SubscribeSend FeedbackThe bare-metal compiler that is shipped with the SoC EDS is the Mentor Graphics Sourcery™

SD Card Boot Utility112014.12.15ug-1137SubscribeSend FeedbackThe SoC EDS SD card boot utility is a tool for updating the boot software on an SD card.T

ContentsIntroduction to SoC Embedded Design Suite... 1-1Overview...

Getting Started Guides42014.12.15ug-1137SubscribeSend FeedbackThis chapter presents a series of getting started guides aimed at enabling you to quickl

Warning: The users of this tool need administrative or root access to their computer to use this tool towrite to physical SD cards. These rights are n

Figure 11-1: Sample Output from Utilityug-11372014.12.15Tool Options11-3SD Card Boot UtilityAltera CorporationSend Feedback

Linux Software Development Tools122014.12.15ug-1137SubscribeSend FeedbackThe following list contains the Linux software development tools:• Linux comp

SD Card Boot UtilityThe SoC EDS SD card boot utility is a tool for updating the boot software on an SD card.The Preloader is typically stored in a cus

Table 12-1: Command Line OptionsCommand line Argument Required? Description-p filename Required Specifies Preloader file to write-b filename Required

Figure 12-1: Sample Output from UtilityDevice Tree GeneratorA Device Tree is a data structure that describes the underlying hardware to an operating s

Yocto PluginThe Yocto Linux Source Package available on the Yocto Project website allows the entire Linux softwarestack (kernel, drivers, device tree,

Support and Feedback132014.12.15ug-1137SubscribeSend FeedbackAltera values your feedback. Please contact your Altera TSFAE or submit a service request

Dual in-line package (DIP) Switch Settings• SW1 = all switches OFF• SW2 = all switches OFF• SW3 = ON-OFF-OFF-OFF-ON-ON. This selects the proper FPGA c

The steps are:1. Setup the board as described in Board Setup section.2. Extract the SD card image from the archive <SoC EDS installation directory&

The Preloader is an essential tool for SoC software. It performs the low-level initialization, brings upSDRAM memory, loads the next boot stage from f

Figure 4-3: Default Options in the BSP Editor window7. Click Generate in the BSP Editor dialog box to generate the Preloader files.8. Click Exit in th

• Cyclone V Device Handbook: Booting and ConfigurationFor more information about Booting and Configuration with regards to Preloader, refer to the Boo

2. Select C/C++ > C Project and click Next.ug-11372014.12.15Create New Project4-7Getting Started GuidesAltera CorporationSend Feedback

3.Edit Project Name to be TestProject, select Project Type to be Bare-metal Executable > EmptyProject, and select Toolchains to be Altera Baremetal

Set the Linker Script1. Go to Project > Propertiesug-11372014.12.15Set the Linker Script4-9Getting Started GuidesAltera CorporationSend Feedback

2. Go to C/C++ Build > Settings > GCC Linker > Image and then click Linker Script.4-10Set the Linker Scriptug-11372014.12.15Altera Corporatio

Importing the Bare-Metal Debugging Sample Application...4-52Compiling the Bare-Metal Debugging Sampl

3. Browse to <SoC EDS installation directory>\host_tools\mentor\gnu\arm\baremetal\arm-altera-eabi\lib\cycloneV-dk-oc-ram-hosted.ld, select cyclo

4. Click OK to close the Project Properties window.Write Application Source Code1. Go to File > New > Source File4-12Write Application Source Co

2.Edit the filename in Source File to be test.c and click Finish.ug-11372014.12.15Write Application Source Code4-13Getting Started GuidesAltera Corpor

3.Edit the test.c file to contain the text shown in the following image.Note:The __auto_semihosting symbol is a convenient way to let Debugger know th

Build Application1. Build the application by going to Project > Build Project.ug-11372014.12.15Build Application4-15Getting Started GuidesAltera Co

2. After the project is built, the Console shows the commands and the Project shows the createdTestProject.axf executable.4-16Build Applicationug-1137

Debug Application1. Setup board.2. Go to Run > Debug Configurationsug-11372014.12.15Debug Application4-17Getting Started GuidesAltera CorporationSe

3. Right-click DS-5 Debugger and click New.4-18Debug Applicationug-11372014.12.15Altera CorporationGetting Started GuidesSend Feedback

4. Select target to be Altera > Cyclone V SoC (Dual Core) > Bare Metal Debug > Debug Cortex-A9_0and Target Connection to be USB-Blaster.ug-11

5. Click the Connection > Browse Button to select the connection to the target board.6. Select the desired target and click Select.4-20Debug Applic

Hardware Handoff Files...7-3Using the P

7. Go to Files tab > Target Configuration > Application on host to download and click the Workspacebutton to browse for the executable in the cu

9. Click the Debug button to download the application and start the debug session.4-22Debug Applicationug-11372014.12.15Altera CorporationGetting Star

10.When Eclipse asks you if you want to switch to Debug perspective, accept by clicking Yes.11.Application will be downloaded and stopped at entry to

12.Click the Continue button or press F8. The application runs to completion and exits. The Applicationconsole shows the message printed by applicatio

Getting Started with ARM Compiler Bare-Metal Project ManagementThis section presents a complete bare-metal example demonstrating the ARM Compiler bare

Figure 4-5: Select a WorkspaceCreate a New Project1. Go to File > New > Project...4-26Create a New Projectug-11372014.12.15Altera CorporationGet

Figure 4-6: New Project2. Select C/C++ > C Project and click Next.ug-11372014.12.15Create a New Project4-27Getting Started GuidesAltera Corporation

Figure 4-7: Create a New C Project3.Edit Project Name to be TestProject. Select Project Type to be Executable > Empty Project; thenToolchains to be

Figure 4-8: Create C ProjectCreate a Linker Script1. Go to File > New > Other...ug-11372014.12.15Create a Linker Script4-29Getting Started Guid

2. Select Scatter File Editor > Scatter File and press Next.4-30Create a Linker Scriptug-11372014.12.15Altera CorporationGetting Started GuidesSend

Support and Feedback...13-1TOC-5Altera Corporation

Figure 4-9: Create a Scatter File3.Select the Test Project, edit the file name to be scatter.scat and click Finish.ug-11372014.12.15Create a Linker Sc

Figure 4-10: Scatter File Resource4. Edit the file "scatter.scat" to contain the following:4-32Create a Linker Scriptug-11372014.12.15Altera

Figure 4-11: Contents of "scatter.scat"The above linker script instructs the linker on how to link the application:• Defines OCRAM base addr

Figure 4-12: Graphical View of the Linker ScriptSet the Linker Script1. Go to Project > Properties.4-34Set the Linker Scriptug-11372014.12.15Altera

Figure 4-13: Test Project Properties2. Go to C/C++ Build > Settings > ARM Linker 5 > Image Layout and then click Browse:ug-11372014.12.15Set

Figure 4-14: Settings3. Select the newly created file "scatter.scat" and click Open.4-36Set the Linker Scriptug-11372014.12.15Altera Corpora

Figure 4-15: Opening the Newly Created File4. Click OK to close the Project Properties window.Write Application Source Code1. Go to File > New >

Figure 4-16: New Source File2. Edit the file name to be "test.c" and click Finish.4-38Write Application Source Codeug-11372014.12.15Altera C

Figure 4-17: New Source File3. Edit the "test.c" file to contain the text shown in the following image:ug-11372014.12.15Write Application So

Figure 4-18: Text for Test .cBuild Application1. Build the application by going to Project > Build Project.4-40Build Applicationug-11372014.12.15Al

Introduction to SoC Embedded Design Suite12014.12.15ug-1137SubscribeSend FeedbackThe Altera® system on a chip (SoC) Embedded Design Suite (EDS) provid

Figure 4-19: Build Project2. The project is built. The console shows the commands, and the project shows the "TestProject.axf"executable tha

Figure 4-20: Console and Project Views CreatedDebug Application1. Setup board.2. Go to Run > Debug Configurations4-42Debug Applicationug-11372014.1

Figure 4-21: Debug Configurations3. Right-click DS-5 Debugger and click New.ug-11372014.12.15Debug Application4-43Getting Started GuidesAltera Corpora

Figure 4-22: New DS-5 Debugger4. Select the "Target" to be Altera > Cyclone V SoC (Dual Core) > Bare Metal Debug > Debug Cortex-A9_

Figure 4-23: Debug Configuration - Connection Tab5. Click the Connection > Browse button to select the connection to the target board.6. Select the

Figure 4-24: Target Connection7. Go to Files tab > Target Configuration > Application on the host to download and click theWorkspace buton to br

Figure 4-25: Target Configuration8. Browse to the executable and click OK.ug-11372014.12.15Debug Application4-47Getting Started GuidesAltera Corporati

Figure 4-26: Open "TestProject.axf"9. Click the Debug button to download the application and start the debug session.4-48Debug Applicationug

Figure 4-27: Debug Session Started10.Eclipse will ask whether to switch to the "Debug" perspective. Accept by clicking Yes.Figure 4-28: Conf

Figure 4-29: DS-5 Debug Window12.Click the Continue button or press F8. The application will run to completion and exit. The applica‐tion console will

The major components of the SoC EDS include:• ARM® Development Studio 5 (DS-5™) Altera Edition (AE) Toolkit• Compiler tool chains:• Bare-metal GNU Com

Figure 4-30: Application ConsoleGetting Started with Bare-Metal DebuggingThe ARM DS-5 Altera Edition provides very powerful bare metal debugging capab

The provided sample application prints a “Hello” message on the debugger console, by using semihosting.This way no pins are used and all communication

Figure 4-31: Import Existing Project3. In the Import Projects dialog box, select the Select Archive File option.4. Click Browse, then navigate to <

Compiling the Bare-Metal Debugging Sample ApplicationThe sample application is compiled using the Mentor bare-metal GCC tool chain invoked by theMakef

The Target is already pre-configured to be Altera > Cyclone VSoC > Bare Metal Debug > Debug Cortex-A9_0via Altera USB-Blaster.3. Click Browse

Figure 4-34: Select Debug Hardware5. Click the Debug button from the bottom of the Debug Configurations dialog box.6. Eclipse ask whether to switch to

Figure 4-35: Program Downloaded7. Click Continue green button (or press F8) to run the application. It displays the hello message in theApplication Co

Figure 4-36: Debugging Session window8. Click Disconnect from Target button to close the debugging session.Getting Started with the Hardware LibraryTh

The sample application is built with a makefile that performs the following steps:1. Copies Hardware Libraries source code from installation folder to

Figure 4-37: Import Existing Project3. In the Import Projects dialog box, select the Select Archive File option.4. Click Browse, then navigate to <

• The socfpga_cyclone5.dtb file is a generic DTB file which does not have any dependency on soft IP.FPGA programming and bridge releasing are not requ

Figure 4-38: Select Imported File5. Click Finish. The project will be imported. The project files will be displayed in the Project Explorerpanel. The

File Name Descriptionaltera-socfpga-hosted.ld Linker scriptdebug-hosted.ds Debugger script use to load the sample applicationMakefile Makefile used to

To run the sample application, perform the following steps:1. In the Eclipse IDE, click Run > Debug Configurations... to open the Debug Configurati

Figure 4-41: Select USB Blaster5. Click the Debug button from the bottom of the Debug Configurations dialog box.6. Eclipse ask whether to switch to De

Figure 4-42: Application Downloaded7. Click Continue green button (or press F8) to run the application. It displays a log of activities itperforms in

Figure 4-43: Application Completed8. Click Disconnect from Target button to close the debugging session.Sequence Sample ApplicationFunctionUsed Hardwa

Sequence Sample ApplicationFunctionUsed HardwareLibraries APIsDescription12 socfpga_bridge_cleanupalt_bridge_uninit Deinitialize bridges13socfpga_fpga

Figure 4-44: Configue Peripheral Register Visibility4. Click the Debug button to download the application to the target board.5. Select the Registers

Figure 4-45: Peripheral Registers6. Put a breakpoint in the source code file named hwlib.c at the line where the soft IP GPIO module dataregister is w

Figure 4-46: Breakpoint Added7. Let the program run by clicking the green Continue button or by pressing F8. The code will stop at thebreakpoint.Note:

This table lists typical tool usage, but your actual requirements depend on your specific project andorganization.Hardware EngineerAs a hardware engin

Figure 4-47: Soft IP Registers11.You can resume the code several times by pressing F8, and you will see how the DATA registerchanges and the HPS LEDs

• Online ARM DS-5 DocumentationThe ARM DS-5 Altera Edition reference material can be accessed online on the documentation page ofthe ARM website (www.

1. Start Embedded Command Shell by running <SoC EDS installation directory>/embedded_command_shell.sh2. Run the following command: cd <SoC ED

Figure 4-48: Configure Connection4. Click on the Debugger and perform the following steps:a. Select option Connect Only for Run Controlb. Check Execut

Figure 4-49: Debugger Settings5. Click the Debug button. The debugger connects to the board, stops the cores as instructed and loadsthe kernel symbols

Figure 4-50: Linux Kernel Stopped6. To view the running threads, maximize the top left panel. It shows Active Threads with the twocurrently executing

Figure 4-51: Linux Threads7. Minimize the Debug Control panel and maximize the Functions panel from top right. All of thefunctions in the kernel are d

Figure 4-52: Kernel Debugger BreakpointsGetting Started with Linux Application DebuggingThe ARM DS-5 Altera Edition provides very powerful Linux appli

The required steps are:1. Setup the board as described in the Getting Started with Board Setup section; and connect the HPSEthernet Connector J2 to th

Figure 4-53: Import Existing Project3. In the Import Projects dialog box, select the Select Archive File option.4. Click Browse, then navigate to <