Altera Nios II Specifications download pdf (Page 248)

stw r4, 0(r5)

flushd 0(r5)

flushi r5

flushp

Note: Notice that this example uses the stw/flushd pair instead of the stwio instruction. The stwio

instruction does not flush the data cache, and therefore might leave stale data in the data cache.

The stw instruction writes the new instruction in r4 to the instruction address specified by r5. If a data

cache is present, the instruction is written just to the data cache and the associated line is marked dirty.

The flushd instruction writes the data cache line associated with the address in r5 to memory and

invalidates the corresponding data cache line. The flushi instruction invalidates the instruction cache

line associated with the address in r5. Finally, the flushp instruction ensures that the processor pipeline

has not prefetched the old instruction at the address specified by r5.

This code sequence is correct for all Nios II implementations. If a Nios II core does not have a particular

kind of cache, the corresponding flush instruction (flushd or flushi) is executed as a nop.

For Users of the HAL

The HAL API does not provide functions for this cache management case.

Managing Cache in Multi-Master and Multi-Processor Systems

The Nios II architecture does not provide hardware cache coherency. Instead, software cache coherency

must be provided when communicating through shared memory. The data cache contents of all

processors accessing the shared memory must be managed by software to ensure that all masters read the

most recent values and do not overwrite new data with stale data. This management is done by using the

data cache flushing and bypassing facilities to move data between the shared memory and the data

cache(s) as needed.

The flushd instruction ensures that the data cache and memory contain the same value for one line. If

the line contains dirty data, it is written to memory. The line is then invalidated in the data cache.

Consistently bypassing the data cache is very important. The processor does not check if an address is in

the data cache when bypassing the data cache. If software cannot guarantee that a particular address is in

the data cache, it must flush the address from the data cache before bypassing it for a load or store. This

action guarantees that the processor does not bypass new (dirty) data in the cache, and mistakenly access

old data in memory.

Bit-31 Cache Bypass

The ldio/stio family of instructions explicitly bypass the data cache. Bit-31 provides an alternate method

to bypass the data cache. Using the bit-31 cache bypass, the normal ld/st family of instructions can be

used to bypass the data cache if the most significant bit of the address (bit 31) is set to one. The value of bit

31 is only used internally to the processor; bit 31 is forced to zero in the actual address accessed. This

limits the maximum byte address space to 31 bits.

Using bit 31 to bypass the data cache is a convenient mechanism for software because the cacheability of

the associated address is contained in the address. This usage allows the address to be passed to code that

uses the normal ld/st family of instructions, while still guaranteeing that all accesses to that address

consistently bypass the data cache.

NII5V2

2015.05.14

For Users of the HAL

9-5

Cache and Tightly-Coupled Memory

Altera Corporation

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