Altera Nios II Specifications

101 Innovation DriveSan Jose, CA 95134www.altera.comNios II Processor Reference HandbookNII5V1-7.2

x Altera Corporation Chapter Revision Dates Nios II Processor Reference Handbook

5–12 Altera CorporationNios II Processor Reference Handbook October 2007Nios II/s CoreJTAG Debug ModuleThe Nios II/f core supports the JTAG debug mod

Altera Corporation 5–13October 2007 Nios II Processor Reference HandbookNios II Core Implementation DetailsThe following sections discuss the notew

5–14 Altera CorporationNios II Processor Reference Handbook October 2007Nios II/s CoreShift and Rotate Performance The performance of shift operation

Altera Corporation 5–15October 2007 Nios II Processor Reference HandbookNios II Core Implementation DetailsInstruction CacheThe instruction cache f

5–16 Altera CorporationNios II Processor Reference Handbook October 2007Nios II/s CoreAccessing tightly-coupled memory bypasses cache memory. The pro

Altera Corporation 5–17October 2007 Nios II Processor Reference HandbookNios II Core Implementation DetailsPipeline StallsThe pipeline is set up so

5–18 Altera CorporationNios II Processor Reference Handbook October 2007Nios II/s CoreException HandlingThe Nios II/s core supports the following exc

Altera Corporation 5–19October 2007 Nios II Processor Reference HandbookNios II Core Implementation DetailsNios II/e CoreThe Nios II/e “economy” co

5–20 Altera CorporationNios II Processor Reference Handbook October 2007Nios II/e Coref For information regarding data cache bypass methods, refer to

Altera Corporation 5–21October 2007 Nios II Processor Reference HandbookNios II Core Implementation DetailsException HandlingThe Nios II/e core sup

Altera Corporation xi About This HandbookIntroductionThis handbook is the primary reference for the Nios®II family of embedded processors. The hand

5–22 Altera CorporationNios II Processor Reference Handbook October 2007Document Revision HistoryDocument Revision HistoryTable 5–12 shows the revisi

Altera Corporation 6–1October 2007 6. Nios II Processor RevisionHistoryIntroductionEach release of the Nios®II Embedded Design Suite (EDS) introd

6–2 Altera CorporationNios II Processor Reference Handbook October 2007Architecture RevisionsTable 6–1 lists the version numbers of all releases of t

Altera Corporation 6–3October 2007 Nios II Processor Reference HandbookNios II Processor Revision Historyinstruction to the instruction set, Altera

6–4 Altera CorporationNios II Processor Reference Handbook October 2007Core Revisions5.1 SP1 January 2006 Bug Fix:Back-to-back store instructions can

Altera Corporation 6–5October 2007 Nios II Processor Reference HandbookNios II Processor Revision HistoryNios II/s CoreTable 6–4 lists revisions to

6–6 Altera CorporationNios II Processor Reference Handbook October 2007JTAG Debug Module RevisionsNios II/e CoreTable 6–5 lists revisions to the Nios

Altera Corporation 6–7October 2007 Nios II Processor Reference HandbookNios II Processor Revision HistoryTable 6–6 lists revisions to the JTAG debu

6–8 Altera CorporationNios II Processor Reference Handbook October 2007Document Revision HistoryDocument Revision HistoryTable 6–7 shows the revision

Altera Corporation 7–1October 2007 7. Application BinaryInterfaceThis section describes the Application Binary Interface (ABI) for the Nios®II

xii Altera CorporationNios II Processor Reference HandbookHow to Find Further InformationHow to Find Further InformationThis handbook is one part of t

7–2 Altera CorporationNios II Processor Reference Handbook User Guide October 2007Memory AlignmentMemory AlignmentContents in memory are aligned a

Altera Corporation 7–3October 2007 Nios II Processor Reference HandbookApplication Binary InterfaceThe endianness of values greater than 8-bits i

7–4 Altera CorporationNios II Processor Reference Handbook User Guide October 2007StacksFigure 7–1. Stack Pointer, Frame Pointer and the Current F

Altera Corporation 7–5October 2007 Nios II Processor Reference HandbookApplication Binary InterfaceFurther Examples of StacksThere are a number o

7–6 Altera CorporationNios II Processor Reference Handbook User Guide October 2007StacksFigure 7–3. Stack Frame Using Variable ArgumentsStack Fram

Altera Corporation 7–7October 2007 Nios II Processor Reference HandbookApplication Binary InterfaceDebuggers can use the knowledge of how the fun

7–8 Altera CorporationNios II Processor Reference Handbook User Guide October 2007Arguments and Return ValuesArguments and Return ValuesThis secti

Altera Corporation 7–9October 2007 Nios II Processor Reference HandbookApplication Binary InterfaceExample 7–2. Example: function a() calls funct

7–10 Altera CorporationNios II Processor Reference Handbook User Guide October 2007Document Revision HistoryDocument Revision HistoryTable 7–3 sho

Altera Corporation 8–1October 2007 8. Instruction Set ReferenceIntroductionThis section introduces the Nios®II instruction-word format and provid

Altera Corporation xiiiNios II Processor Reference HandbookAbout This HandbookTypographical ConventionsThis document uses the typographic conventions

8–2 Altera CorporationNios II Processor Reference Handbook October 2007Word FormatsR-TypeThe defining characteristic of the R-type instruction-word f

Altera Corporation 8–3October 2007 Nios II Processor Reference HandbookInstruction Set ReferenceJ-TypeJ-type instructions contain: A 6-bit opcode

8–4 Altera CorporationNios II Processor Reference Handbook October 2007Instruction OpcodesInstruction OpcodesThe OP field in the Nios II instruction

Altera Corporation 8–5October 2007 Nios II Processor Reference HandbookInstruction Set ReferenceTable 8–2. OPX Encodings for R-Type InstructionsOPX

8–6 Altera CorporationNios II Processor Reference Handbook October 2007Assembler Pseudo-instructionsAssembler Pseudo-instructionsTable 8–3 lists pseu

Altera Corporation 8–7October 2007 Nios II Processor Reference HandbookInstruction Set ReferenceAssembler MacrosThe Nios II assembler provides macr

8–8 Altera CorporationNios II Processor Reference Handbook October 2007Instruction Set ReferenceInstruction Set ReferenceThe following pages list all

Altera Corporation 8–9October 2007 Nios II Processor Reference HandbookaddaddaddOperation:rC← rA + rBAssembler Syntax:add rC, rA, rBExample:add r6,

8–10 Altera CorporationNios II Processor Reference Handbook October 2007addiaddiadd immediateOperation:rB← rA + σ (IMM16)Assembler Syntax:addi rB, rA

Altera Corporation 8–11October 2007 Nios II Processor Reference Handbookandandbitwise logical andOperation:rC← rA & rBAssembler Syntax:and rC,

xiv Altera CorporationNios II Processor Reference HandbookTypographical Conventions

8–12 Altera CorporationNios II Processor Reference Handbook October 2007andhiandhibitwise logical and immediate into high halfwordOperation:rB← rA &a

Altera Corporation 8–13October 2007 Nios II Processor Reference Handbookandiandibitwise logical and immediateOperation:rB← rA & (0x0000 : IMM16

8–14 Altera CorporationNios II Processor Reference Handbook October 2007beqbeqbranch if equal Operation: if (rA == rB)then PC← PC + 4 + σ (IMM16)else

Altera Corporation 8–15October 2007 Nios II Processor Reference Handbookbgebgebranch if greater than or equal signedOperation: if ((signed) rA >

8–16 Altera CorporationNios II Processor Reference Handbook October 2007bgeubgeubranch if greater than or equal unsigned Operation: if ((unsigned) rA

Altera Corporation 8–17October 2007 Nios II Processor Reference Handbookbgtbgtbranch if greater than signed Operation: if ((signed) rA > (signed

8–18 Altera CorporationNios II Processor Reference Handbook October 2007bgtubgtubranch if greater than unsignedOperation: if ((unsigned) rA > (uns

Altera Corporation 8–19October 2007 Nios II Processor Reference Handbookbleblebranch if less than or equal signedOperation: if ((signed) rA <= (

8–20 Altera CorporationNios II Processor Reference Handbook October 2007bleubleubranch if less than or equal to unsignedOperation: if ((unsigned) rA

Altera Corporation 8–21October 2007 Nios II Processor Reference Handbookbltbltbranch if less than signedOperation: if ((signed) rA < (signed) rB

Altera Corporation Section I–1 Section I. Nios IIProcessorThis section provides information about the Nios® II processor. This section includes the

8–22 Altera CorporationNios II Processor Reference Handbook October 2007bltubltubranch if less than unsignedOperation: if ((unsigned) rA < (unsign

Altera Corporation 8–23October 2007 Nios II Processor Reference Handbookbnebnebranch if not equalOperation: if (rA != rB)then PC← PC + 4 + σ (IMM16

8–24 Altera CorporationNios II Processor Reference Handbook October 2007brbrunconditional branchOperation:PC ← PC + 4 + σ (IMM16)Assembler Syntax:br

Altera Corporation 8–25October 2007 Nios II Processor Reference Handbookbreakbreakdebugging breakpointOperation:bstatus←statusPIE← 0U← 0ba← PC + 4

8–26 Altera CorporationNios II Processor Reference Handbook October 2007bretbretbreakpoint returnOperation:status← bstatusPC← baAssembler Syntax:bret

Altera Corporation 8–27October 2007 Nios II Processor Reference Handbookcallcallcall subroutineOperation:ra← PC + 4PC← (PC31..28 : IMM26 × 4)Assem

8–28 Altera CorporationNios II Processor Reference Handbook October 2007callrcallrcall subroutine in registerOperation:ra← PC + 4PC← rAAssembler Synt

Altera Corporation 8–29October 2007 Nios II Processor Reference Handbookcmpeqcmpeqcompare equalOperation: if (rA == rB)then rC← 1else rC← 0Assemble

8–30 Altera CorporationNios II Processor Reference Handbook October 2007cmpeqicmpeqicompare equal immediateOperation: if (rA σ (IMM16))then rB← 1else

Altera Corporation 8–31October 2007 Nios II Processor Reference Handbookcmpgecmpgecompare greater than or equal signedOperation: if ((signed) rA &g

Section I–2 Altera Corporation Nios II Processor Nios II Processor Reference Handbook

8–32 Altera CorporationNios II Processor Reference Handbook October 2007cmpgeicmpgeicompare greater than or equal signed immediateOperation: if ((sig

Altera Corporation 8–33October 2007 Nios II Processor Reference Handbookcmpgeucmpgeucompare greater than or equal unsignedOperation: if ((unsigned)

8–34 Altera CorporationNios II Processor Reference Handbook October 2007cmpgeuicmpgeuicompare greater than or equal unsigned immediateOperation: if (

Altera Corporation 8–35October 2007 Nios II Processor Reference Handbookcmpgtcmpgtcompare greater than signedOperation: if ((signed) rA > (signe

8–36 Altera CorporationNios II Processor Reference Handbook October 2007cmpgticmpgticompare greater than signed immediateOperation: if ((signed) rA &

Altera Corporation 8–37October 2007 Nios II Processor Reference Handbookcmpgtucmpgtucompare greater than unsignedOperation: if ((unsigned) rA >

8–38 Altera CorporationNios II Processor Reference Handbook October 2007cmpgtuicmpgtuicompare greater than unsigned immediateOperation: if ((unsigned

Altera Corporation 8–39October 2007 Nios II Processor Reference Handbookcmplecmplecompare less than or equal signedOperation: if ((signed) rA <=

8–40 Altera CorporationNios II Processor Reference Handbook October 2007cmpleicmpleicompare less than or equal signed immediateOperation: if ((signed

Altera Corporation 8–41October 2007 Nios II Processor Reference Handbookcmpleucmpleucompare less than or equal unsignedOperation: if ((unsigned) rA

Altera Corporation 1–1October 2007 1. IntroductionIntroductionThis chapter is an introduction to the Nios®II embedded processor family. This chap

8–42 Altera CorporationNios II Processor Reference Handbook October 2007cmpleuicmpleuicompare less than or equal unsigned immediateOperation: if ((un

Altera Corporation 8–43October 2007 Nios II Processor Reference Handbookcmpltcmpltcompare less than signedOperation: if ((signed) rA < (signed)

8–44 Altera CorporationNios II Processor Reference Handbook October 2007cmplticmplticompare less than signed immediateOperation: if ((signed) rA <

Altera Corporation 8–45October 2007 Nios II Processor Reference Handbookcmpltucmpltucompare less than unsignedOperation: if ((unsigned) rA < (un

8–46 Altera CorporationNios II Processor Reference Handbook October 2007cmpltuicmpltuicompare less than unsigned immediateOperation: if ((unsigned) r

Altera Corporation 8–47October 2007 Nios II Processor Reference Handbookcmpnecmpnecompare not equalOperation: if (rA != rB)then rC← 1else rC← 0Asse

8–48 Altera CorporationNios II Processor Reference Handbook October 2007cmpneicmpneicompare not equal immediateOperation: if (rA != σ (IMM16))then rB

Altera Corporation 8–49October 2007 Nios II Processor Reference Handbookcustomcustomcustom instructionOperation: if c == 1then rC← fN(rA, rB, A, B,

8–50 Altera CorporationNios II Processor Reference Handbook October 2007divdivdivideOperation:rC← rA ÷ rBAssembler Syntax:div rC, rA, rBExample:div r

Altera Corporation 8–51October 2007 Nios II Processor Reference Handbookdivudivudivide unsignedOperation:rC← rA ÷ rBAssembler Syntax:divu rC, rA, r

1–2 Altera CorporationNios II Processor Reference Handbook October 2007Getting Started with the Nios II ProcessorA Nios II processor system is equiva

8–52 Altera CorporationNios II Processor Reference Handbook October 2007ereteretexception returnOperation:status← estatusPC← eaAssembler Syntax:eretE

Altera Corporation 8–53October 2007 Nios II Processor Reference Handbookflushdflushdflush data cache lineOperation: Flushes the data cache line ass

8–54 Altera CorporationNios II Processor Reference Handbook October 2007flushdaflushdaflush data cache addressOperation: Flushes the data cache line

Altera Corporation 8–55October 2007 Nios II Processor Reference Handbookflushiflushiflush instruction cache lineOperation: Flushes the instruction-

8–56 Altera CorporationNios II Processor Reference Handbook October 2007flushpflushpflush pipelineOperation: Flushes the processor pipeline of any pr

Altera Corporation 8–57October 2007 Nios II Processor Reference Handbookinitdinitdinitialize data cache lineOperation: Initializes the data cache l

8–58 Altera CorporationNios II Processor Reference Handbook October 2007initiinitiinitialize instruction cache lineOperation: Initializes the instruc

Altera Corporation 8–59October 2007 Nios II Processor Reference Handbookjmpjmpcomputed jumpOperation:PC← rAAssembler Syntax:jmp rAExample:jmp r12De

8–60 Altera CorporationNios II Processor Reference Handbook October 2007jmpijmpijump immediateOperation:PC← (PC31..28 : IMM26 × 4)Assembler Syntax:j

Altera Corporation 8–61October 2007 Nios II Processor Reference Handbookldb / ldbioldb / ldbioload byte from memory or I/O peripheralOperation:rB←

Altera Corporation 1–3October 2007 Nios II Processor Reference HandbookIntroductionFigure 1–1. Example of a Nios II Processor SystemIf the prototyp

8–62 Altera CorporationNios II Processor Reference Handbook October 2007ldbu / ldbuioldbu / ldbuioload unsigned byte from memory or I/O peripheral Op

Altera Corporation 8–63October 2007 Nios II Processor Reference Handbookldh / ldhioldh / ldhioload halfword from memory or I/O peripheralOperation:

8–64 Altera CorporationNios II Processor Reference Handbook October 2007ldhu / ldhuioldhu / ldhuioload unsigned halfword from memory or I/O periphera

Altera Corporation 8–65October 2007 Nios II Processor Reference Handbookldw / ldwioldw / ldwioload 32-bit word from memory or I/O peripheralOperati

8–66 Altera CorporationNios II Processor Reference Handbook October 2007movmovmove register to register Operation:rC← rAAssembler Syntax:mov rC, rAEx

Altera Corporation 8–67October 2007 Nios II Processor Reference Handbookmovhimovhimove immediate into high halfwordOperation:rB← (IMMED : 0x0000)As

8–68 Altera CorporationNios II Processor Reference Handbook October 2007movimovi move signed immediate into wordOperation:rB← σ (IMMED)Assembler Synt

Altera Corporation 8–69October 2007 Nios II Processor Reference Handbookmoviamoviamove immediate address into wordOperation:rB← labelAssembler Syn

8–70 Altera CorporationNios II Processor Reference Handbook October 2007movuimovuimove unsigned immediate into wordOperation:rB← (0x0000 : IMMED)Asse

Altera Corporation 8–71October 2007 Nios II Processor Reference HandbookmulmulmultiplyOperation:rC← (rA × rB) 31..0Assembler Syntax:mul rC, rA, rBE

Copyright © 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-ig

1–4 Altera CorporationNios II Processor Reference Handbook October 2007Configurable Soft-Core Processor ConceptsBecause the pins and logic resources

8–72 Altera CorporationNios II Processor Reference Handbook October 2007mulimulimultiply immediateOperation:rB← (rA × σ(IMM16)) 31..0Assembler Syntax

Altera Corporation 8–73October 2007 Nios II Processor Reference Handbookmulxssmulxssmultiply extended signed/signedOperation:rC← ((signed) rA) × ((

8–74 Altera CorporationNios II Processor Reference Handbook October 2007mulxsumulxsumultiply extended signed/unsignedOperation:rC← ((signed) rA) × ((

Altera Corporation 8–75October 2007 Nios II Processor Reference Handbookmulxuumulxuumultiply extended unsigned/unsignedOperation:rC← ((unsigned) rA

8–76 Altera CorporationNios II Processor Reference Handbook October 2007nextpcnextpcget address of following instructionOperation:rC← PC + 4Assembler

Altera Corporation 8–77October 2007 Nios II Processor Reference Handbooknopnopno operationOperation: None Assembler Syntax:nopExample:nopDescriptio

8–78 Altera CorporationNios II Processor Reference Handbook October 2007nornorbitwise logical norOperation:rC← ~(rA | rB)Assembler Syntax:nor rC, rA,

Altera Corporation 8–79October 2007 Nios II Processor Reference Handbookororbitwise logical orOperation:rC← rA | rBAssembler Syntax:or rC, rA, rBEx

8–80 Altera CorporationNios II Processor Reference Handbook October 2007orhiorhibitwise logical or immediate into high halfwordOperation:rB← rA | (IM

Altera Corporation 8–81October 2007 Nios II Processor Reference Handbookorioribitwise logical or immediateOperation:rB← rA | (0x0000 : IMM16)Assemb

Altera Corporation 1–5October 2007 Nios II Processor Reference HandbookIntroductionFlexible Peripheral Set and Address MapA flexible peripheral set

8–82 Altera CorporationNios II Processor Reference Handbook October 2007rdctlrdctlread from control registerOperation:rC← ctlNAssembler Syntax:rdctl

Altera Corporation 8–83October 2007 Nios II Processor Reference Handbookretretreturn from subroutineOperation:PC← raAssembler Syntax:retExample:ret

8–84 Altera CorporationNios II Processor Reference Handbook October 2007rolrolrotate leftOperation:rC← rA rotated left rB4..0 bit positionsAssembler

Altera Corporation 8–85October 2007 Nios II Processor Reference Handbookrolirolirotate left immediateOperation:rC← rA rotated left IMM5 bit positio

8–86 Altera CorporationNios II Processor Reference Handbook October 2007rorrorrotate rightOperation:rC ← rA rotated right rB4..0 bit positionsAssemb

Altera Corporation 8–87October 2007 Nios II Processor Reference Handbooksllsllshift left logicalOperation:rC← rA << (rB4..0)Assembler Syntax:

8–88 Altera CorporationNios II Processor Reference Handbook October 2007sllisllishift left logical immediateOperation:rC← rA << IMM5Assembler S

Altera Corporation 8–89October 2007 Nios II Processor Reference Handbooksrasrashift right arithmeticOperation:rC← (signed) rA >> ((unsigned)

8–90 Altera CorporationNios II Processor Reference Handbook October 2007sraisraishift right arithmetic immediateOperation:rC← (signed) rA >> ((

Altera Corporation 8–91October 2007 Nios II Processor Reference Handbooksrlsrlshift right logicalOperation:rC← (unsigned) rA >> ((unsigned) r

1–6 Altera CorporationNios II Processor Reference Handbook October 2007OpenCore Plus EvaluationBecause the processor is implemented on reprogrammable

8–92 Altera CorporationNios II Processor Reference Handbook October 2007srlisrlishift right logical immediateOperation:rC← (unsigned) rA >> ((u

Altera Corporation 8–93October 2007 Nios II Processor Reference Handbookstb / stbiostb / stbiostore byte to memory or I/O peripheralOperation:Mem8[

8–94 Altera CorporationNios II Processor Reference Handbook October 2007sth / sthiosth / sthiostore halfword to memory or I/O peripheral Operation:Me

Altera Corporation 8–95October 2007 Nios II Processor Reference Handbookstw / stwiostw / stwiostore word to memory or I/O peripheralOperation:Mem32

8–96 Altera CorporationNios II Processor Reference Handbook October 2007subsubsubtractOperation:rC← rA – rBAssembler Syntax:sub rC, rA, rBExample:sub

Altera Corporation 8–97October 2007 Nios II Processor Reference Handbooksubisubisubtract immediateOperation:rB← rA – σ (IMMED)Assembler Syntax:subi

8–98 Altera CorporationNios II Processor Reference Handbook October 2007syncsyncmemory synchronizationOperation: NoneAssembler Syntax:syncExample:syn

Altera Corporation 8–99October 2007 Nios II Processor Reference HandbooktraptraptrapOperation:estatus← statusPIE← 0U← 0ea← PC + 4PC← exception han

8–100 Altera CorporationNios II Processor Reference Handbook October 2007wrctlwrctlwrite to control registerOperation:ctlN← rAAssembler Syntax:wrctl

Altera Corporation 8–101October 2007 Nios II Processor Reference Handbookxorxorbitwise logical exclusive orOperation:rC← rA ^ rBAssembler Syntax:xo

Altera Corporation 1–7October 2007 Nios II Processor Reference HandbookIntroductionReferenced DocumentsThis chapter references the following docume

8–102 Altera CorporationNios II Processor Reference Handbook October 2007xorhixorhibitwise logical exclusive or immediate into high halfwordOperation

Altera Corporation 8–103October 2007 Nios II Processor Reference Handbookxorixoribitwise logical exclusive or immediateOperation:rB ← rA ^ (0x0000

8–104 Altera CorporationNios II Processor Reference Handbook October 2007Referenced DocumentsReferenced DocumentsThis chapter references no other doc

1–8 Altera CorporationNios II Processor Reference Handbook October 2007Document Revision History

Altera Corporation 2–1October 2007 2. Processor ArchitectureIntroductionThis chapter describes the hardware structure of the Nios®II processor, i

2–2 Altera CorporationNios II Processor Reference Handbook October 2007Processor ImplementationFigure 2–1. Nios II Processor Core Block DiagramThe Ni

Altera Corporation 2–3October 2007 Nios II Processor Reference HandbookProcessor Architectureinstruction set, not a particular hardware implementat

2–4 Altera CorporationNios II Processor Reference Handbook October 2007Arithmetic Logic UnitArithmetic Logic UnitThe Nios II arithmetic logic unit (A

Altera Corporation 2–5October 2007 Nios II Processor Reference HandbookProcessor ArchitectureFloating Point InstructionsThe Nios II architecture su

Altera Corporation iii ContentsChapter Revision Dates ... ixAbout This Han

2–6 Altera CorporationNios II Processor Reference Handbook October 2007Reset Signals1 The floating point custom instructions can be added to any Nios

Altera Corporation 2–7October 2007 Nios II Processor Reference HandbookProcessor ArchitectureThe software can enable and disable any interrupt sour

2–8 Altera CorporationNios II Processor Reference Handbook October 2007Memory and I/O Organizationf For an explanation of the instruction reference f

Altera Corporation 2–9October 2007 Nios II Processor Reference HandbookProcessor Architecturef For details that affect programming issues, see the

2–10 Altera CorporationNios II Processor Reference Handbook October 2007Memory and I/O OrganizationMemory and Peripheral AccessThe Nios II architectu

Altera Corporation 2–11October 2007 Nios II Processor Reference HandbookProcessor ArchitectureData Master PortThe Nios II data bus is implemented a

2–12 Altera CorporationNios II Processor Reference Handbook October 2007Memory and I/O Organizationcore. The cache memories can improve the average m

Altera Corporation 2–13October 2007 Nios II Processor Reference HandbookProcessor ArchitectureIf an application always requires certain data or sec

2–14 Altera CorporationNios II Processor Reference Handbook October 2007Memory and I/O Organizationinstruction and data access. Each tightly-coupled

Altera Corporation 2–15October 2007 Nios II Processor Reference HandbookProcessor ArchitectureJTAG Debug ModuleThe Nios II architecture supports a

iv Altera CorporationNios II Processor Reference HandbookContentsMemory and I/O Organization ...

2–16 Altera CorporationNios II Processor Reference Handbook October 2007JTAG Debug ModuleDownload and Execute SoftwareDownloading software refers to

Altera Corporation 2–17October 2007 Nios II Processor Reference HandbookProcessor ArchitectureArmed Triggers The JTAG debug module provides a two-l

2–18 Altera CorporationNios II Processor Reference Handbook October 2007JTAG Debug ModuleTrace CaptureTrace capture refers to ability to record the i

Altera Corporation 2–19October 2007 Nios II Processor Reference HandbookProcessor ArchitectureTrace FramesA “frame” is a unit of memory allocated f

2–20 Altera CorporationNios II Processor Reference Handbook October 2007Document Revision HistoryDocument Revision HistoryTable 2–6 shows the revisio

Altera Corporation 3–1October 2007 3. Programming ModelIntroductionThis chapter describes the Nios®II programming model, covering processor featu

3–2 Altera CorporationNios II Processor Reference Handbook October 2007Control Registersaccessed by call and ret instructions. C and C++ compilers us

Altera Corporation 3–3October 2007 Nios II Processor Reference HandbookProgramming Model1 When writing to control registers, all undefined bits mus

3–4 Altera CorporationNios II Processor Reference Handbook October 2007Operating ModesbstatusThe bstatus register holds a saved copy of the status re

Altera Corporation 3–5October 2007 Nios II Processor Reference HandbookProgramming ModelThe following sections define the modes and the transitions

Altera Corporation vNios II Processor Reference HandbookContentsChapter 4. Instantiating the Nios II Processor in SOPC BuilderIntroduction ...

3–6 Altera CorporationNios II Processor Reference Handbook October 2007Exception Processing Instruction-related exceptionsTable 3–4 shows all possib

Altera Corporation 3–7October 2007 Nios II Processor Reference HandbookProgramming ModelThe reset state is undefined for all other system component

3–8 Altera CorporationNios II Processor Reference Handbook October 2007Exception Processing3. Writes the address of the instruction following the bre

Altera Corporation 3–9October 2007 Nios II Processor Reference HandbookProgramming ModelFigure 3–1. Relationship Between ienable, ipending, PIE and

3–10 Altera CorporationNios II Processor Reference Handbook October 2007Exception ProcessingInstruction-Related ExceptionsInstruction-related excepti

Altera Corporation 3–11October 2007 Nios II Processor Reference HandbookProgramming ModelOther ExceptionsThe previous sections describe all of the

3–12 Altera CorporationNios II Processor Reference Handbook October 2007Exception ProcessingDetermining the Cause of Interrupt and Instruction-Relate

Altera Corporation 3–13October 2007 Nios II Processor Reference HandbookProgramming Modelaccess to the code memory to read this address). If the in

3–14 Altera CorporationNios II Processor Reference Handbook October 2007Memory and Peripheral AccessOn the other hand, hardware interrupt exceptions

Altera Corporation 3–15October 2007 Nios II Processor Reference HandbookProgramming ModelCode written for a processor core with cache memory behave

vi Altera CorporationNios II Processor Reference HandbookContentsInstruction Performance ...

3–16 Altera CorporationNios II Processor Reference Handbook October 2007Instruction Set CategoriesThe data transfer instructions in Table 3–6 support

Altera Corporation 3–17October 2007 Nios II Processor Reference HandbookProgramming ModelMove InstructionsThese instructions provide move operation

3–18 Altera CorporationNios II Processor Reference Handbook October 2007Instruction Set CategoriesShift and Rotate InstructionsThe following instruct

Altera Corporation 3–19October 2007 Nios II Processor Reference HandbookProgramming ModelProgram Control InstructionsThe Nios II architecture suppo

3–20 Altera CorporationNios II Processor Reference Handbook October 2007Instruction Set CategoriesThe conditional-branch instructions do not have del

Altera Corporation 3–21October 2007 Nios II Processor Reference HandbookProgramming ModelCustom InstructionsThe custom instruction provides low-lev

3–22 Altera CorporationNios II Processor Reference Handbook October 2007Document Revision History Application Binary Interface chapter of the Nios I

Altera Corporation 4–1October 2007 4. Instantiating the Nios IIProcessor in SOPC BuilderIntroductionThis chapter describes the Nios®II Processor

4–2 Altera CorporationNios II Processor Reference Handbook October 2007Core Nios II PageCore Nios II PageThe Core Nios II page presents the main sett

Altera Corporation 4–3October 2007 Nios II Processor Reference HandbookInstantiating the Nios II Processor in SOPC BuilderThe following sections de

Altera Corporation viiNios II Processor Reference HandbookContentsR-Type ...

4–4 Altera CorporationNios II Processor Reference Handbook October 2007Core Nios II Page None - This option conserves logic resources by eliminating

Altera Corporation 4–5October 2007 Nios II Processor Reference HandbookInstantiating the Nios II Processor in SOPC BuilderOffset allows you to spec

4–6 Altera CorporationNios II Processor Reference Handbook October 2007Caches and Memory Interfaces PageCaches and Memory Interfaces PageThe Caches a

Altera Corporation 4–7October 2007 Nios II Processor Reference HandbookInstantiating the Nios II Processor in SOPC BuilderThe following sections de

4–8 Altera CorporationNios II Processor Reference Handbook October 2007Caches and Memory Interfaces PageData Master SettingsThe Data Master settings

Altera Corporation 4–9October 2007 Nios II Processor Reference HandbookInstantiating the Nios II Processor in SOPC BuilderAdvanced Features PageThe

4–10 Altera CorporationNios II Processor Reference Handbook October 2007JTAG Debug Module PageReset SignalsInclude cpu_resetrequest and cpu_resettake

Altera Corporation 4–11October 2007 Nios II Processor Reference HandbookInstantiating the Nios II Processor in SOPC BuilderTable 4–1 describes the

4–12 Altera CorporationNios II Processor Reference Handbook October 2007JTAG Debug Module PageThe following sections describe the configuration setti

Altera Corporation 4–13October 2007 Nios II Processor Reference HandbookInstantiating the Nios II Processor in SOPC BuilderTable 4–2 on page 4–13 i

viii Altera CorporationNios II Processor Reference HandbookContents

4–14 Altera CorporationNios II Processor Reference Handbook October 2007Custom Instructions PageAdvanced Debug SettingsDebug levels 3 and 4 support t

Altera Corporation 4–15October 2007 Nios II Processor Reference HandbookInstantiating the Nios II Processor in SOPC Builderby implementing performa

4–16 Altera CorporationNios II Processor Reference Handbook October 2007Custom Instructions Page1 To display custom instructions in the table of acti

Altera Corporation 4–17October 2007 Nios II Processor Reference HandbookInstantiating the Nios II Processor in SOPC BuilderFloating Point Hardware

4–18 Altera CorporationNios II Processor Reference Handbook October 2007Custom Instructions PageFigure 4–6. Nios II Floating Point Hardware Dialog Bo

Altera Corporation 4–19October 2007 Nios II Processor Reference HandbookInstantiating the Nios II Processor in SOPC Builderf For details integratin

4–20 Altera CorporationNios II Processor Reference Handbook October 2007Document Revision HistoryDocument Revision HistoryTable 4–3 shows the revisio

Altera Corporation Section II–1 Section II. AppendicesThis section provides additional information about the Nios® II processor.This section includ

Section II–2 Altera Corporation Appendices Nios II Processor Reference Handbook

Altera Corporation 5–1October 2007 5. Nios II CoreImplementation DetailsIntroductionThis document describes all of the Nios®II processor core imp

Altera Corporation ix Chapter Revision DatesThe chapters in this book, Nios II Processor Reference Handbook, were revised on the following dates. W

5–2 Altera CorporationNios II Processor Reference Handbook October 2007IntroductionInstruction BusCache – 512 bytes to 64 KBytes512 bytes to 64 KByte

Altera Corporation 5–3October 2007 Nios II Processor Reference HandbookNios II Core Implementation DetailsDevice Family SupportAll Nios II cores pr

5–4 Altera CorporationNios II Processor Reference Handbook October 2007Nios II/f CoreOverviewThe Nios II/f core: Has separate instruction and data c

Altera Corporation 5–5October 2007 Nios II Processor Reference HandbookNios II Core Implementation Details1 The performance of the embedded multipl

5–6 Altera CorporationNios II Processor Reference Handbook October 2007Nios II/f Coreaddi r1, r1, 100 ; r1 = r1 + 100 (Depends on result of mul)Shift

Altera Corporation 5–7October 2007 Nios II Processor Reference HandbookNios II Core Implementation DetailsBoth the instruction and data cache addre

5–8 Altera CorporationNios II Processor Reference Handbook October 2007Nios II/f CoreThe Nios II/f core implements all the data cache bypass methods.

Altera Corporation 5–9October 2007 Nios II Processor Reference HandbookNios II Core Implementation DetailsAccessing tightly-coupled memory bypasses

5–10 Altera CorporationNios II Processor Reference Handbook October 2007Nios II/f CoreOnly the A-stage and D-stage are allowed to create stalls.The A

Altera Corporation 5–11October 2007 Nios II Processor Reference HandbookNios II Core Implementation DetailsExecution performance for all instructio