Altera Phase-Locked Loop Reconfiguration IP Core User Manual download pdf (Page 9)

Functional Description—Implementing Multiple Reconfiguration Using an External ROM Page 9

Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation

After this, the

reconfig

signal can be asserted for 1 clock cycle to reconfigure the PLL

to the intended settings that have been written to the scan cache of the

ALTPLL_RECONFIG megafunction (refer to Figure 6).

If you assert the

reset

rom

address

signal, the

write

rom

ena

signal is deasserted for

1 clock cycle and the

rom_address_out

signal resets. When the

write

rom

ena

gets

asserted, the write process then restarts from address

(refer to Figure 7).

Figure 6. Completing Write to the Scan Cache of the ALTPLL_RECONFIG Megafunction from the ROM

(1)

Note to Figure 6:

(1) This figure also shows the beginning of the reconfiguration process.

Figure 7. Asserting the reset_rom_address Signal

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 50 51

No comments

Altera Phase-Locked Loop Reconfiguration IP Core User Manual Page 9