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Altera GPIO User Manual Page 13

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Data Interface Signals and Corresponding Clocks
The following table shows the data interface signals and the corresponding clocks.
Table 3: Data Interface Signals and Corresponding Clocks
Signal Name Configuration Clock
din
Register Mode: Simple
Register/DDIO
ck
Half-rate: not used
Separate Clocks: Off
Register Mode: DDIO
ck_hrHalf rate: used
Separate Clocks: off
Register Mode: Simple
Register/DDIO
ck_in
Half rate: not used
Separate Clocks: on
Register Mode: DDIO
ck_hr_inHalf rate: used
Separate Clocks: on
dout/oe
Register Mode: Simple
Register/DDIO
ck
Half rate: not used
Separate Clocks: off
Register Mode: DDIO
ck_hrHalf rate: used
Separate Clocks: off
Register Mode: Simple
Register/DDIO
ck_out
Half rate: not used
Separate Clocks: on
Register Mode: DDIO
ck_hr_outHalf rate: used
Separate Clocks: on
ug-altera_gpio
2014.08.18
Data Interface Signals and Corresponding Clocks
13
Altera GPIO IP Core User Guide
Altera Corporation
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