Altera LVDS SERDES User Manual

Altera LVDS SERDES IP Core User Guide2014.08.18ug_altera_lvdsSubscribeSend FeedbackThe Altera LVDS SERDES IP Core configures the serializer/deserializ

DescriptionTypeDirectionWidthSignal NameThe clock that drives the core logic feeding theserializer. Not available in the external PLLmode.ClockOutput1

Parameter SettingsYou can parameterize the Altera LVDS SERDES IP core using the IP Parameter Editor.General Settings TabDescriptionValueParameterSpeci

PLL Settings TabDescriptionValueParameterWhen enabled, the IP core does not instantiate aPLL locally. Instead, a series of clock connectionsare elabor

DescriptionValueParameterWhen enabled, this parameter exposes the rx_bitslip_reset port (one input per channel), whichyou can use to reset the bitslip

DescriptionValueParameterWhen enabled, the Altera LVDS SERDES IP coredrives the rx_dpa_locked signal low when the DPAchanges phase selection from the

DescriptionValueParameterSpecifies the closest achievable receiver inclockphase shift to the desired receiver inclock phaseshift.Legal values aredepen

DescriptionValueParameterSpecifies the closest achievable tx_outclock phaseshift to the desired tx_outclock phase shift.Legal values aredependent on t

Specifying phase shift values greater than 360° will change the MSB location within the parallel data.By default, the MSB from the serial data will no

Figure 7: 0° Edge Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8Use 180° to specify the tx_outclock phase to center aligned to t

Figure 10: 180° Center Aligned tx_outclock x8 Serializer Waveform with Division Factor of 2TimingTo properly perform timing analysis on the Altera LVD

DescriptionFunctional ModeIn this mode, you must ensure the correct clock-data alignment, as theincoming data is captured at the bitslip with the fclk

Table 7: Timing FilesDescriptionFileThis .sdc allows the Fitter to optimize timingmargins with timing driven compilation. Alsoallows the TimeQuest tim

Where:• RSKM—is the timing margin between the receiver's clock input and the data input SW.• Time unit interval (TUI)—is the time period of the s

Data Rate: 1 Gbps, Board channel-to-channel skew = 200 psRCCS = 100 ps (pending characterization)SW = 300 ps (pending characterization)TUI = 1000 psTo

Obtaining TCCS ReportFor LVDS transmitters, the TimeQuest Timing Analyzer provides a TCCS report, which shows TCCS valuesfor serial output ports.To ob

Timing ClosureTiming Violation in Internal FPGA PathsAn LVDS SERDES design with high frequency and low SERDES factor is prone to have challenges at cl

To specify an exact device to use, run the following script:quartus_sh -t make_qii_design.tcl [device_name]This script generates a qii directory conta

6. Replace your ALTLVDS_TX or ALTLVDS_RX IP core instantiation in RTL with the Altera LVDS SERDESIP core.The Altera LVDS SERDES IP core port names may

Document Revision HistoryTable 11: Document Revision HistoryChangesVersionDate• Clarified that you must wait five core clock cycles before checkingif

Figure 1: Altera LVDS SERDES Channel DiagramDIN DOUTDOUT DIN DOUT DINDOUT DINClockMultiplexer3lvds_loadenlvds_fclkrx_coreclockIOPLL8 Serial LVDSClock

Clock DomainModesBlockPathDPADPA FIFO and Soft-CDR modesDPA CircuitryRX Data PathLVDS-DPA domain crossingDPA-FIFO modeDPA FIFOLVDSNon-DPA and DPA-FIFO

DPA FIFOIn DPA-FIFO mode, the DPA FIFO synchronizes the retimed data to the high-speed LVDS clock domain.Because the DPA clock may shift phase during

Initializing the Altera LVDS SERDES IP CoreWith the Altera LVDS SERDES IP core, the PLL must be locked to the reference clock prior to using theSERDES

The bitslip circuit can be reset using the rx_bitslip_reset port. This circuit can be reset anytime and isnot dependent on the PLL or DPA circuit oper

SignalsThe following tables list the input and output signals for the Altera LVDS SERDES IP core.N represents the LVDS interface width and the number

DescriptionTypeDirectionWidthSignal NameReceiver parallel data output. Synchronousto rx_coreclock in (DPA-FIFO and non-DPA modes). In soft-CDR mode, e