Altera MAX 10 FPGA User Manual

MAX 10 FPGA Configuration User GuideSubscribeSend FeedbackUG-M10CONFIG2015.05.04101 Innovation DriveSan Jose, CA 95134www.altera.com

Instruction Instruction Code DescriptionISC_ENABLE_HIZ (1)10 1100 1100• Puts the device in ISP mode, tri-states all I/O pins,and drives all core drive

Instruction Instruction Code DescriptionBGP_ENABLE 01 1001 1001• Sets the device to the real-time ISP mode.• Allows access to the internal flash confi

Configuration Settings Description Default State/ValueAllow encrypted POF only If enabled, configuration error will occur ifunencrypted .pof is used.D

Remote System Upgrade FlowBoth the application configuration images, image 0 and image 1, are stored in the CFM. The MAX 10device loads either one of

Remote System Upgrade CircuitryFigure 2-4: Remote System Upgrade CircuitryStatus Register (SR)PreviousStateRegister 2Bit[31..0]StateRegister 1Bit[31..

Core Signal Name LogicalSignalNameInput/OutputDescriptionRU_DOUT regout OutputUse this signal to get output data from the shift register. Datais clock

Table 2-7: Control Inputs to the Remote System Upgrade CircuitryRemote System Upgrade Circuitry Control InputsOperationModeInput Settings for Register

Bits Name Description11:0 Reserved Reserved—set to 0.Remote System Upgrade Status RegistersTable 2-9: Remote System Upgrade Status Register—Current St

User Watchdog TimerThe user watchdog timer prevents a faulty application configuration from stalling the device indefinitely.You can use the timer to

Related Information• Altera Dual Configuration IP Core Avalon-MM Address Map on page 5-1• Avalon Interface SpecificationsProvides more information abo

ContentsMAX 10 FPGA Configuration Overview...1-1MAX 10 FPGA Configuration Schemes and Feature

Unique Chip IDUnique chip ID provides the following features:• Identifies your device in your design as part of a security feature to protect your des

Related Information• JTAG Instruction Availability on page 2-17• Configuration Flash Memory Permissions on page 2-18• .pof Generation through Convert

• Encryption and Decryption on page 2-15Configuration Flash Memory PermissionsThe JTAG secure mode and verify protect features determines the CFM oper

Configuration Error DetectionIn configuration mode, a frame-based CRC is stored in the configuration data and contains the CRC valuefor each data fram

Table 2-15: Error Detection Registers for MAX 10 DevicesRegister Description32-bit signature registerThis register contains the CRC signature. The sig

Table 2-17: Minimum and Maximum Error Detection Frequencies for MAX 10 Devices—PreliminaryDevice Error Detection Frequency Maximum ErrorDetectionFrequ

Recovering from CRC ErrorsThe system that MAX 10 resides in must control device reconfiguration. After detecting an error on theCRC_ERROR pin, strobin

Configuration DetailsConfiguration SequenceFigure 2-10: Configuration Sequence for MAX 10 DevicesPower supplies including VCCIO, VCCA and VCCreach rec

Related Information.pof Generation through Convert Programming Files on page 3-6Provides more information about how to set th weak pull-up during conf

Table 2-21: POR Requirements and Timing for MAX 10 DevicesInstant-On POR Delay Setting Ramp Rate Requirement (tRAMP) POR Delay (tPOR)Enabled Don’t Car

MAX 10 FPGA Configuration IP Core Implementation Guides... 4-1Altera Unique Chip ID IP Core...

Configuration Pin Input/Output Configuration SchemeDEV_OE Input only Optional, JTAG and internal configurationsCONF_DONE Bidirectional, open-drain JTA

MAX 10 FPGA Configuration Design Guidelines32015.05.04UG-M10CONFIGSubscribeSend FeedbackDual-Purpose Configuration PinsGuidelines: Dual-Purpose Config

Pins GuidelinesTDO• If you intend to switch back and forth between user I/O pins and JTAG pin functionsusing the JTAGEN pin, all JTAG pins must be ass

• AN 425: Using the Command-Line Jam STAPL Solution for Device ProgrammingJTAG Configuration SetupTo configure MAX 10 device using a download cable, c

JTAGENIf you use the JTAGEN pin, Altera recommends the following settings:• Once you entered user mode and JTAG pins are regular I/O pins—connect the

• Select the internal configuration scheme• Generate the .pof with ICB settings• Program the .pof the internal flashRelated Information• Internal Conf

Internal ConfigurationMode.pof Generation and ICBSetting MethodDescriptionSingle CompressedImage with MemoryInitialization.Convert ProgrammingFiles• U

Note: The JTAG Secure feature will be disabled by default in Quartus II. If you are interested inusing the JTAG Secure feature, contact Altera for sup

• To program any of the CFM0/CFM1/CFM2 only, select the corresponding CFM in the Program/Configure column.• To program the UFM only, select the UFM in

In user mode, MAX 10 devices support the CHANGE_EDREG JTAG instruction, which allows you to write tothe 32-bit storage register. You can use .jam to a

MAX 10 FPGA Configuration Overview12015.05.04UG-M10CONFIGSubscribeSend FeedbackYou can configure MAX® 10 configuration RAM (CRAM) using the following

Figure 3-2: Error Detection Block Diagram with Interfaces for MAX 10 DevicesClock Divider(1 to 256 Factor)Pre-Computed CRC(Saved in the Option Registe

• Before design compilation—using the Compiler Settings menu.• After design compilation—using the Convert Programming Files option.Enabling Compressio

Generating .ekp File and Encrypt Configuration FileTo generate the .ekp file and encrypt your configuration file, follow these steps:1. On the File me

• Adding key with a .key file.The .key file is a plain text file in which each line represents a key unless the line starts with "#". The&qu

• JEDEC STAPL Format (.jam)• Jam STAPL Byte Code (.jbc)• Serial Vector Format (.svf)10.Type the file name in the File name field, or browse to and sel

Once the .ekp is integrated into the .pof, you can to save the integrated .pof into a new .pof. This newlysaved file will have original .pof integrate

Configura‐tion ImageModeCFM0 (image 0)Encryption KeyCFM1 (image 1)Encryption KeyKey Storedin the DeviceAllowEncryptedPOF OnlyCONFIG_SELpinDesign Loade

CFM0 (image 0)Encryption KeyKey Stored in theDeviceAllow Encrypted POFOnlyDesign Loaded After Power-upKey Y No key Enabled Configuration FailKey Y Key

MAX 10 FPGA Configuration IP CoreImplementation Guides42015.05.04UG-M10CONFIGSubscribeSend FeedbackAltera Unique Chip ID IP CoreThis section provides

Instantiating the Altera Dual Configuration IP CoreTo instantiate the Altera Dual Configuration IP Core, follow these steps:1. On the Tools menu of th

MAX 10 FPGA Configuration Schemes andFeatures22015.05.04UG-M10CONFIGSubscribeSend FeedbackConfiguration SchemesFigure 2-1: High-Level Overview of JTAG

Altera Dual Configuration IP Core References52015.05.04UG-M10CONFIGSubscribeSend FeedbackAltera Dual Configuration IP Core Avalon-MM Address MapTable

Offset R/W Width(Bits)Description2 W 32• Bit 0—trigger read operation from the user watchdog.• Bit 1—trigger read operation from the previous state ap

• Avalon Interface SpecificationsProvides more information about the Avalon-MM interface specifications applied in Altera DualConfiguration IP Core.•

Altera Unique Chip ID IP Core References62015.05.04UG-M10CONFIGSubscribeSend FeedbackAltera Unique Chip ID IP Core PortsTable 6-1: Altera Unique Chip

Additional Information for MAX 10 FPGAConfiguration User GuideA2015.05.04UG-M10CONFIGSubscribeSend Feedback© 2015 Altera Corporation. All rights reser

Document Revision History for MAX 10 FPGA Configuration User GuideDate Version ChangesMay 2015 2015.05.04• Rearranged and updated Configuration Settin

Date Version ChangesDecember 2014 2014.12.15• Rename BOOT_SEL pin to CONFIG_SEL pin.• Update Altera IP Core name from Dual Boot IP Core to AlteraDual

JTAG PinsTable 2-1: JTAG PinPin Function DescriptionTDI Serial input pin for:• instructions• test data• programming data• TDI is sampled on the rising

The internal configuration scheme for 10M02 device supports the following mode:• Single Compressed Image• Single Uncompressed ImageRelated Information

Figure 2-2: Configuration Flash Memory Sectors Utilization for all MAX 10 Devices Except for the10M02 DeviceUnutilized CFM1 and CFM2 sectors can be us

The following are the generic flow of an ISP operation:1. Check ID—the JTAG ID is checked before any program or verify process. The time required to r