Altera Clock Control Block IP Core User Manual Page 26
- Page / 26
- Table of contents
- BOOKMARKS
- User Guide 1
- Contents 3
- 1. About this Megafunction 5
- Device Support 6
- 2. Parameter Settings 7
- MegaWizard Parameter Settings 8
- Notes to Table 2–1: 10
- 3. Functional Description 13
- Global Clock Control Block 14
- Regional Clock Control Block 15
- Clock Enable Signals 16
- Connectivity Restrictions 17
- Input Ports 19
- Output Ports 19
- Verilog HDL Prototype 20
- VHDL Component Declaration 20
- VHDL LIBRARY-USE Declaration 21
- Additional Information 23
- How to Contact Altera 24
- Typographic Conventions 25
- Info–4 Additional Information 26
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