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Altera DDR SDRAM Controller User Manual

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101 Innovation Drive
San Jose, CA 95134
www.altera.com
DDR and DDR2 SDRAM Controller Compiler User
Guide
Software Version: 9.0
Document Date: March 2009
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1 2 3 4 5 6 ... 105 106

Summary of Contents

Page 1 - Document Date: March 2009

101 Innovation DriveSan Jose, CA 95134www.altera.comDDR and DDR2 SDRAM Controller Compiler UserGuideSoftware Version: 9.0Document Date: March 2009

Page 2 - UG-DDRSDRAM-10.0

1–6 Chapter 1: About This CompilerInstallation and LicensingDDR and DDR2 SDRAM Controller Compiler User Guide March 2009 Altera CorporationFigure 1–2

Page 3 - Contents

C–2DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation1 Some of these constraints may conflict with constraints added by

Page 4

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideD. Maximizing PerformanceTo achieve maximum performance, your design

Page 5 - 1. About This Compiler

D–2Adjust the PLL PhasesDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationAdjust the PLL PhasesThere is no automatic se

Page 6 - General Description

D–3Update the PLL Phases© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideUpdate the PLL PhasesAfter compilation you sh

Page 7 - Note to Figure 1–1:

D–4Update the PLL PhasesDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 8 - Note to Table 1–3:

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuidePreliminaryAdditional InformationRevision HistoryThe following table

Page 9 - Installation and Licensing

Info–ii Additional InformationTypographic ConventionsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationPreliminaryVisua

Page 10 - OpenCore Plus Evaluation

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide2. Getting StartedDesign FlowThe Altera DDR and DDR2 SDRAM Controller

Page 11 - 2. Getting Started

2–2 Chapter 2: Getting StartedSOPC Builder Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationThe DDR and DDR

Page 12 - SOPC Builder Design Flow

Chapter 2: Getting Started 2–3SOPC Builder Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideCreate a New Qu

Page 13

2–4 Chapter 2: Getting StartedSOPC Builder Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation1 If you are ta

Page 14 - Parameterize

Chapter 2: Getting Started 2–5SOPC Builder Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide6. Turn on Adva

Page 15 - Add/Update Component

2–6 Chapter 2: Getting StartedSOPC Builder Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationSOPC Builder ge

Page 16 - Create Your Top-Level Design

Chapter 2: Getting Started 2–7SOPC Builder Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideEdit the PLLThe

Page 17 - Edit the PLL

2–8 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporationc

Page 18 - Program a Device

Chapter 2: Getting Started 2–9MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide2

Page 19

Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device design

Page 20

2–10 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 21

Chapter 2: Getting Started 2–11MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

Page 22

2–12 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 23

Chapter 2: Getting Started 2–13MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

Page 24 - Figure 2–1. System Naming

2–14 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 25 - Generate

Chapter 2: Getting Started 2–15MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

Page 26

2–16 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 27 - Simulate the Example Design

Chapter 2: Getting Started 2–17MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

Page 28

2–18 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 29 - Notes to Table 2–2:

Chapter 2: Getting Started 2–19MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

Page 30 - Notes to Table 2–3:

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideContentsChapter 1. About This CompilerRelease Information . . . .

Page 31 - Notes to Table 2–4:

2–20 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 32 - Compile the Example Design

Chapter 2: Getting Started 2–21MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

Page 33

2–22 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 34 - Implement Your Design

Chapter 2: Getting Started 2–23MegaWizard Plug-In Manager Design Flow© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide

Page 35 - Set Up Licensing

2–24 Chapter 2: Getting StartedMegaWizard Plug-In Manager Design FlowDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 36

Chapter 2: Getting Started 2–25Set Up Licensing© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideSet Up LicensingYou ne

Page 37 - Control Logic

2–26 Chapter 2: Getting StartedSet Up LicensingDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 38 - Datapath

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide3. Functional DescriptionThe DDR and DDR2 SDRAM controllers instantia

Page 39

3–2 Chapter 3: Functional DescriptionBlock DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable 3–1 shows

Page 40

Chapter 3: Functional Description 3–3OpenCore Plus Time-Out Behavior© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideI

Page 41 - Device-Level Description

ivDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationMegaCore Verification . . . . . . . . . . . . . . . . . . . . . .

Page 42 - Figure 3–3. Datapath Timing

3–4 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationAll mega

Page 43 - Designing Your Own Controller

Chapter 3: Functional Description 3–5Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideIn the w

Page 44 - DQS Group Block Diagrams

3–6 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure 3

Page 45 - Notes to Figure 3–4:

Chapter 3: Functional Description 3–7Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideDesignin

Page 46 - Notes to Figure 3–5:

3–8 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationThe cont

Page 47 - Notes to Figure 3–6:

Chapter 3: Functional Description 3–9Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFigure 3

Page 48 - Notes to Figure 3–7:

3–10 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure

Page 49 - PLL Configurations

Chapter 3: Functional Description 3–11Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFigure

Page 50 - Stratix II Device

3–12 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure

Page 51 - Cyclone Device

Chapter 3: Functional Description 3–13Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuidePLL Con

Page 52 - Example Design

March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide1. About This CompilerRelease InformationTable 1–1 provides information

Page 53 - Notes to Table 3–5:

3–14 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFor Str

Page 54

Chapter 3: Functional Description 3–15Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFigure

Page 55 - Interface Description

3–16 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationDLL Con

Page 56 - Figure 3–13. Writes

Chapter 3: Functional Description 3–17Device-Level Description© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFigure

Page 57 - Interfaces & Signals

3–18 Chapter 3: Functional DescriptionDevice-Level DescriptionDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationThe tes

Page 58 - [1] [3][2] [5][4]

Chapter 3: Functional Description 3–19Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFor Str

Page 59 - [1] [2] [3] [4] [6][5]

3–20 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationWritesF

Page 60 - User Refresh Control

Chapter 3: Functional Description 3–21Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide1. The

Page 61

3–22 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation1. The

Page 62

Chapter 3: Functional Description 3–23Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide4. The

Page 63 - 200 clock cycles

1–2 Chapter 1: About This CompilerFeaturesDDR and DDR2 SDRAM Controller Compiler User Guide March 2009 Altera CorporationFeatures Support for industr

Page 64

3–24 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation2. The

Page 65 - Note to Table 3–7:

Chapter 3: Functional Description 3–25Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideDDR SDR

Page 66

3–26 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation2. An E

Page 67 - Parameters

Chapter 3: Functional Description 3–27Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide1. The

Page 68

3–28 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationSignals

Page 69 - Controller

Chapter 3: Functional Description 3–29Interfaces & Signals© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideTable 3

Page 70

3–30 Chapter 3: Functional DescriptionInterfaces & SignalsDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable 3

Page 71 - Note to Table 3–15:

Chapter 3: Functional Description 3–31Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideParametersThe paramet

Page 72

3–32 Chapter 3: Functional DescriptionParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationMemoryTable 3–11 show

Page 73 - Controller Timings

Chapter 3: Functional Description 3–33Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideController Table 3–13

Page 74 - Memory Timings

Chapter 1: About This Compiler 1–3General DescriptionMarch 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideThe DDR SDRAM Cont

Page 75 - Board Timings

3–34 Chapter 3: Functional DescriptionParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable 3–14 shows the

Page 76 - Project Settings

Chapter 3: Functional Description 3–35Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideTable 3–15 shows the

Page 77 - Hardware Testing

3–36 Chapter 3: Functional DescriptionParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable 3–16 shows the

Page 78 - (MT46V8M16-75Z)

Chapter 3: Functional Description 3–37Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideTable 3–17 shows the

Page 79 - A. Manual Timing Settings

3–38 Chapter 3: Functional DescriptionParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFor minimum timing re

Page 80

Chapter 3: Functional Description 3–39Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideBoard TimingsTable 3–

Page 81

3–40 Chapter 3: Functional DescriptionParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationProject SettingsTable

Page 82 - Resynchronization

Chapter 3: Functional Description 3–41MegaCore Verification© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideManual Tim

Page 83 - Resynchronization Registers

3–42 Chapter 3: Functional DescriptionMegaCore VerificationDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable 3–26

Page 84 - Notes to Figure A–2:

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideA. Manual Timing SettingsParametersTable A–1 shows the resynchronizat

Page 85 - Notes to Figure A–3:

1–4 Chapter 1: About This CompilerPerformance and Resource UtilizationDDR and DDR2 SDRAM Controller Compiler User Guide March 2009 Altera Corporation

Page 86 - Notes to Figure A–4:

A–2ParametersDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable A–2 shows the postamble options (DQS mode only).f

Page 87 - Note to Figure A–5:

A–3Parameters© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideTable A–3 shows the capture options (non-DQS mode only).

Page 88 - DQS Postamble

A–4ResynchronizationDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationTable A–4 shows the timing analysis options. Resy

Page 89 - Postamble Logic

A–5Resynchronization© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideResynchronization RegistersFigure A–1 shows the r

Page 90 - Postamble

A–6ResynchronizationDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure A–2 shows the resynchronization registers

Page 91 - Examples

A–7Resynchronization© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideFigure A–4 shows the resynchronization registers

Page 92

A–8ResynchronizationDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure A–4 shows the resynchronization registers

Page 93

A–9Resynchronization© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideTable A–5 shows the manual resynchronization para

Page 94

A–10DQS PostambleDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationIntermediate Resynchronization RegistersFigure A–6 s

Page 95 - Board, Cyclone II Edition

A–11DQS Postamble© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideThe DDR and DDR2 SDRAM Controller Compiler provides

Page 96

Chapter 1: About This Compiler 1–5Installation and LicensingMarch 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideThe perform

Page 97

A–12DQS PostambleDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationFigure A–8 shows an example of how to choose the bes

Page 98

A–13Examples© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideExamplesExample A–1 and Example A–2 show the generated PL

Page 99

A–14ExamplesDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera CorporationExample A–3 and Example A–4 show the top-level design fil

Page 100

A–15Examples© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideExample A–4 shows the top-level example design file with

Page 101 - D. Maximizing Performance

A–16ExamplesDDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 102 - Place the Fedback PLL

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideB. DDR SDRAM on the Nios DevelopmentBoard, Cyclone II EditionThis app

Page 103 - Update the PLL Phases

B–2DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation3. The DDR SDRAM device on the Nios Development Board, Cyclone II

Page 104

B–3© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide6. The DDR SDRAM wizard automatically creates constraint scripts f

Page 105 - Additional Information

B–4DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Page 106 - Preliminary

© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User GuideC. HardCopy II Design WalkthroughThis walkthrough explains the additi

Related models: DDR2 SDRAM Controller

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