Altera Stratix II User's Guide download pdf (Page 38)

38 Altera Corporation

Stratix II Professional Filtering Lab

5. Right-click on adder_result_tap and select Unsigned Decimal as

the radix, as shown in Figure 28.

Figure 28. Specify the Radix as Unsigned Decimal for adder_result_tap

6. In the Select your JTAG cable list, select USB-Blaster.

7. To run the analyzer, click Start Analysis. DSP Builder runs a Tcl

script to instruct the SignalTap II logic analyzer to begin analyzing

the data and wait for the trigger conditions to occur.

8. Press SW4 (see Figure 29) on the Stratix II EP2S180 DSP

development board to generate a pulse on the reset input signal.

9. Press SW5 (see Figure 29) on the Stratix II EP2S180 DSP

development board to assert clken and to enable the counter

circuit. Setting the clken input signal high after generating a pulse

on the reset input signal ensures that the trigger condition, the first

falling edge of count_reached, occurs no sooner than 4,095 clock

cycles after the design has been reset. This minimum delay

requirement of 4,095 clock cycles allows the data at the output of the

anti-aliasing filter sufficient time to stabilize before the SignalTap II

logic analyzer begins acquiring data.

1 2 ... 33 34 35 36 37 38 39 40 41 42 43

No comments

Altera Stratix II User's Guide Page 38