Altera Stratix II User's Guide download pdf (Page 37)

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Exercise 4: Analyze & Compare the Results in Hardware

Configure the EP2S180 FPGA With the Filtering Lab Design

To configure the EP2S180 FPGA, follow these steps:

1. Double-click the SignalCompiler block (see Figure 22).

2. In the SignalCompiler 5.0.1 - page 1 of 2 dialog box, turn on Re-run

update diagram to solve workspace parameters.

3. Click Analyze.

4. In the SignalCompiler 5.0.1 - page 2 of 2 dialog box, under

Hardware Compilation, under Single step compilation, click

1 - Convert MDL to VHDL. SignalCompiler generates a tool

command language (Tcl) script that you can use in “Perform

SignalTap II Analysis”.

1 The filtering lab design is precompiled at the factory. Therefore,

you can skip the synthesis and fitting steps. If you choose to

recompile the design, you have to run IP Toolbench for all three

IP blocks (NCO_1MHz, NCO_10MHz, and in the FIR_3MHz

blocks) as described in “Exercise 1: Review the Filtering Lab

Design” on page 4, click Finish in the Parameterize step, and

Generate to regenerate the design.

5. Click 4 - Program Device to configure the EP2S180 FPGA.

6. Click OK to exit the SignalCompiler window.

Perform SignalTap II Analysis

In filter_design.mdl, to specify the falling edge as the trigger condition

for count_reached_tap, follow these steps:

1. Double-click the SignalTap II Analysis block. The SignalTap II logic

analyzer displays all of the nodes connected to SignalTap II blocks

as signals to be analyzed.

2. Click count_reached_tap under Signal Name.

3. Choose Falling Edge in the Trigger Condition list.

4. Click Change. The condition is updated.

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Altera Stratix II User's Guide Page 37