Altera Stratix II User Manual download pdf (Page 9)

Altera Corporation 9

Stratix FPGA Family Errata Sheet

On-Chip Termination Value Tolerance

The specification for on-chip termination in Stratix devices has been

updated. The series and parallel on-chip termination circuitry does

not conform to the initial specification and is not functional. The on-

chip termination circuitry for differential termination is functional

and the resistance accuracy is shown in Table 2.

Note to Table 2:

(1) See the Stratix Device Family Data Sheet in Volume 1 of the Stratix Device Handbook for more detailed specifications.

The Stratix device on-chip termination circuitry will not be updated.

Designers should not use series and parallel on-chip termination in

Stratix devices. Altera recommends using external resistors.

Differential on-chip termination is functional and should be used

with appropriate simulations.

Revision History

The information contained in the Stratix FPGA Family Errata Sheet

version 2.5 supersedes information published in previous versions.

Version 2.5

The Stratix FPGA Family Errata Sheet version 2.5 contains the

following changes.

■ Updated Table 1 with on-chip termination information.

■ Updated the "On-Chip Termination Value Tolerance" section.

Table 2. Stratix Differential Termination Performance

On-Chip

Termination Type

Accuracy Specification Notes

Min Typ Max Unit

Series Not functional Designs must use external resistors.

Parallel Not functional Designs must use external resistors.

Differential (LVDS) 110 137.5 165 Ω Commercial temperature grade devices

(1)

100 135 170 Ω Industrial temperature grade devices (1)

1 2 3 4 5 6 7 8 9 10

No comments

Altera Stratix II User Manual Page 9