4 Altera Corporation
Stratix FPGA Family Errata Sheet
Release Clears Before Tri-States
When the RELEASE_CLEARS_BEFORE_TRI_STATES option is used with
EP1S25 revision A and B devices, registers clocked by internal global clock
nets (including PLL outputs) will power up in an unknown state instead
of the state specified by the user.
When the RELEASE_CLEARS_BEFORE_TRI_STATES option is turned
on, the designer must reset the device to operate correctly.
The RELEASE_CLEARS_BEFORE_TRI_STATES configuration option
directs the device to release the clear signal on registered logic cells and
I/O cells before releasing the output enable override on tri-state buffers.
If this option is turned off, the output enable signals are released before
the clear overrides are released. This option will be turned off by default.
When the designer turns this option on, the Quartus II software generates
the following warning message: “Release clears before tri-states option is
turned on. If you are using EP1S25 revision A or B devices, contact Altera
Applications.”
EP1S10 &
EP1S25 High
Power-Up
Current Issue
EP1S10 ES devices typically require a 750-mA current on the V
CCINT
voltage supply to successfully power up. EP1S25 ES devices typically
require a 2.5-A current on the V
CCINT
voltage supply to successfully
power up the device. Designers should select power supplies and
regulators that can supply this amount of current when designing with
EP1S10 and EP1S25 ES devices.
EP1S25 production devices are fixed and require significantly less power-
up current.
f
For more information on EP1S10 devices, contact Altera Applications.
Stratix
Industrial
Temperature
Grade Device
Issues
The PLL lock circuit in Stratix industrial temperature grade devices is not
functional when the ambient temperature is below –20 °C and the PFD
frequency is at or below 200 MHz.
To work around this issue, choose a higher input frequency and an N
counter value such that the input frequency to the PFD (inclk/N) is
above 200 MHz. This will guarantee correct operation of the LOCK signal.
1 Although the LOCK signal on the enhanced and fast PLL toggles
under the conditions outlined above, the PLL is still in LOCK and
the output clock is within specifications. This issue is a limitation
of the LOCK circuit inside the Stratix PLLs.
(58 pages)
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comments to this Manuals