Altera Stratix II User Manual download pdf (Page 6)

6 Altera Corporation

Stratix FPGA Family Errata Sheet

Figure 2. Gated Lock in Internal Logic Circuit

Figure 3 shows the simulation waveform of the gated lock signal.The

gated_lock signal transitions high on the 10

clock cycle and is driven

low after the PLL loses lock. The toggle signal frequency decreases as the

frequency of the PLL begins to drift.

Figure 3. Gated Lock Signal Simulation Waveform

1 2 3 4 5 6 7 8 9 10

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Altera Stratix II User Manual Page 6