Altera Stratix II User Manual

®November 2003, ver. 2.5 Errata SheetAltera Corporation 1StratixFPGA FamilyES-STXFPGA-2.5This errata sheet provides updated information on StratixTM

Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, thestylized Altera logo, specific device designa

2 Altera CorporationStratix FPGA Family Errata SheetNotes to Table 1:(1) Contact Altera Applications for information on EP1S10 devices regarding this

Altera Corporation 3Stratix FPGA Family Errata SheetWhen designing with Stratix EP1S10 devices, designers must use the EP1S10 ES ordering codes in th

4 Altera CorporationStratix FPGA Family Errata SheetRelease Clears Before Tri-StatesWhen the RELEASE_CLEARS_BEFORE_TRI_STATES option is used with EP1S

Altera Corporation 5Stratix FPGA Family Errata SheetStratix Family IssuesThe following issues affect all Stratix devices. Gated lock (GLOCK) Enhan

6 Altera CorporationStratix FPGA Family Errata SheetFigure 2. Gated Lock in Internal Logic CircuitFigure 3 shows the simulation waveform of the gated

Altera Corporation 7Stratix FPGA Family Errata SheetEnhanced PLL Clock Switchover GlitchThe CLKBAD0 and CLKBAD1 signals have a design flaw that cause

8 Altera CorporationStratix FPGA Family Errata SheetFigure 4. Clock Switchover CircuitFigure 5 shows the simulation waveform of the PLL switching even

Altera Corporation 9Stratix FPGA Family Errata SheetOn-Chip Termination Value ToleranceThe specification for on-chip termination in Stratix devices h