Altera DE2-115 User Manual

My First FPGA for Altera DE2-115 Board數位電路實驗TA: 吳柏辰Author: Trumen

Notepad++ (2/5)1012345

Notepad++ (3/5)11Column Mode Editing1. Alt + Mouse dragging2. Alt + Shift + Arrow keys

Notepad++ (4/5)121234

Notepad++ (5/5)13

Assign The Device14

Introduction to FPGA (1/3)• A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a designer after manufacturin

Introduction to FPGA (2/3)• FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnec

Introduction to FPGA (3/3)• Xilinx and Altera are the current FPGA market leaders and long-time industry rivals.• Both Xilinx and Altera provide free

Altera's Main FPGA Products• Stratix series FPGAs are the largest, highest bandwidth devices, with up to 1.1 million logic elements.• Cyclone ser

Altera® Development Kits• Development kits include software, reference designs, cables, and programming hardware (development board).19http://www.alte

Outline• Complete Your Verilog Design • Assign The Device• Add a PLL Megafunction• Assign the Pins• Create a Default TimeQuest SDC File• Compile and V

Installed The USB-Blaster driver (1/3)• Plug in the 12-volt adapter to provide power to the board. • Use the USB cable to connect the leftmost USB con

Installed The USB-Blaster driver (2/3)• The computer will recognize the new hardware connected to its USB port.• But it will be unable to proceed if i

Installed The USB-Blaster driver (3/3)• If the New Hardware Wizard does not appear, check the website below ⇓22http://www.altera.com/download/drivers/

Setup Licensing (1/2)2312

Setup Licensing (2/2)2412Make sure these items appear, and now you can compile your design.Only for IP 140.112.*.*

Create a New Project25123

26123same as (top-level) file name

27123

2812for DE2-1153

29

Complete Your Verilog Design 3

301234

31123

Add a PLL Megafunction32

Using Quartus Add a PLL Megafunction• A PLL uses the on-board oscillator (50 MHz for DE2-115 Board) to create a constant clock frequency as the input

3412

351

361

37123

38123for DE2-115

39Uncheck all the options1

exp1_traffic.v (1/5)4module exp1_traffic (clk, rst_n,pause, HEX0);//==== parameter definition ===============================// for finite state mach

401

411

421

4312

4412

Assign the Pins45

Assign the Pins• Before making pin assignments…46123

4712

48Type “M23”, then push Enter12Now, you are finished creating your Quartus II design!for DE2-115

Create a Default TimeQuest SDC File49

exp1_traffic.v (2/5)5//==== reg/wire declaration ================================//-------- output --------------------------------------reg [6:0] HEX

Create a Default TimeQuestSDC File• Timing settings are critically important for a successful design. • For this tutorial you will create a basic Syno

5112

5212

53create_clock -period 20 [get_ports clk]create_clock -period 62.5 -name clk_16derive_pll_clocksderive_clock_uncertaintyset_input_delay 0 -clock clk_1

541234

Compile and Verify Your Design55

Compile Your Design• After creating your design you must compile it. • Compilation converts the design into a bitstream that can be downloaded into th

571

Compilation Report• Make sure there is no error.58

Program the FPGA Device• After compiling and verifying your design you are ready to program the FPGA on the development board. • You download the SOF

exp1_traffic.v (3/5)6// finite state machine (state)always@(*) begincase(state) S_NORMAL: beginif(pause==1) next_state = S_PAUSE;else next_state = S_N

6012

611

6212

631

64~~Finish~~

Demo Video• 10 seconds countdown system65

Configuring the Cyclone IV E FPGA66

Configuring the FPGA• JTAG programming• AS programming67In this method of programming, named after the IEEE standards Joint Test Action Group, the con

JTAG Chain (1/2)• To use JTAG interface for configuring FPGA device, the JTAG chain on DE2-115 must form a close loop that allows Quartus II programme

JTAG Chain (2/2)• Shorting pin1 and pin2 on JP3 can disable the JTAG signals on HSMC connector that will form a close JTAG loop chain on DE2-115 board

exp1_traffic.v (4/5)7// 7-segment Displaysalways@(*) begincase(countdown)7'd0: next_HEX0 = 7'b1000000;7'd1: next_HEX0 = 7'b1111001

Configuring the FPGA in JTAG Mode (1/2)• This figure illustrates the JTAG configuration setup.70

Configuring the FPGA in JTAG Mode (2/2)1. Ensure that power is applied to the DE2-115 board.2. Configure the JTAG programming circuit by setting the R

Configuring the EPCS64 in AS Mode (1/2)• This figure illustrates the AS configuration setup.72

Configuring the EPCS64 in AS Mode (2/2)1. Ensure that power is applied to the DE2-115 board.2. Connect the supplied USB cable to the USB Blaster port

Programmer Object File• Programmer Object File is a binary file (with the extension .pof) containing the data for programming a configuration device.•

12755693for DE2-115478

1762345

7712

78~~Finish~~

The End.Any question?

exp1_traffic.v (5/5)8//==== sequential part ===================================== always@( posedge clk_16 or negedge rst_n ) beginif( rst_n==0 ) begi

Reference1. http://en.wikipedia.org/wiki/Field-programmable_gate_array2. "My First FPGA for Altera DE2-115 Board" by Terasic Technologies In

Notepad++ (1/5)9Highlight123