Chapter 3: 10GBASE-R PHY IP Core 3–5

Parameter Settings

March 2012 Altera Corporation Altera Transceiver PHY IP Core

User Guide

Analog Options

The following sections explain how to specify analog options for Stratix IV and

Stratix V devices.

Stratix IV Devices

For Stratix IV devices, you specify analog options on the Analog Options tab.

Table 3–6 describes these options.

PLL type

CMU

ATX

You can select either the CMU or ATX PLL. The CMU PLL has a larger

frequency range than the ATX PLL. The ATX PLL is designed to

improve jitter performance and achieves lower channel-to-channel

skew; however, it supports a narrower range of data rates and

reference clock frequencies. Another advantage of the ATX PLL is

that it does not use a transceiver channel, while the CMU PLL does.

Because the CMU PLL is more versatile, it is specified as the default

setting. An informational message displays in the message pane

telling you whether the chosen settings for Data rate and Input clock

frequency are legal for the CMU PLL, or for both the CMU and ATX

PLLs.

Reference Clock Frequency

322.265625 MHz

644.53125 MHz

Stratix V devices support both frequencies. Stratix IV GX devices

only support 644.53125 MHz.

Additional Options

Use external PMA control and

reconfig

On/Off

For Stratix IV devices, if you turn this option on, the PMA controller

and reconfiguration block are external, rather than included

10GBASE-R PHY IP core, allowing you to use the same PMA

controller and reconfiguration IP cores for other protocols in the

same transceiver quad.

When you turn this option On, the

cal_blk_powerdown

(0x021)

and

pma_tx_pll_is_locked

(0x022) registers are available.

Enable additional control and

status pins

On/Off

If you turn this option on, the following 2 signals are brought out to

the top level of the IP core to facilitate debugging:

hi_ber

and

block_lock

Enable rx_recovered_clk pin On/Off

When you turn this option on, the RX recovered clock signal is an

output signal.

Starting channel number 0–96

For Stratix IV devices, specifies the starting channel number. Must be

0 or a multiple of 4. You only need to set this parameter if you are

using external PMA and reconfiguration modules. This option is only

necessary for Stratix IV devices.

Table 3–5. General Options (Part 2 of 2)

Name Value Description

Table 3–6. PMA Analog Options (Part 1 of 2)

Name Value Description

Transmitter termination

resistance

OCT_85_OHMS

OCT_100_OHMS

OCT_120_OHMS

OCT_150_OHMS

Indicates the value of the termination resistor for the transmitter.

Transmitter VOD control setting 0–7 Sets V

for the various TX buffers.

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 229 230

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Altera PHY IP Core User's Guide Page 23

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