Altera PHY IP Core User's Guide

101 Innovation DriveSan Jose, CA 95134www.altera.com UG-01080-1.6User GuideAltera Transceiver PHY IP CoreDocument last updated for Altera Complete Des

1–2 Chapter 1: IntroductionPCSAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideFigure 1–1 illustrates the top level modules that

6–18 Chapter 6: PHY IP Core for PCI Express (PIPE)Simulation Files and Example TestbenchAltera Transceiver PHY IP Core March 2012 Altera CorporationUs

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide7. Custom PHY IP CoreThe Altera Custom PHY IP core is a generic PHY that you can

7–2 Chapter 7: Custom PHY IP CoreDevice Family SupportAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideFigure 7–1 illustrates the

Chapter 7: Custom PHY IP Core 7–3Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideParameter SettingsTo configur

7–4 Chapter 7: Custom PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuidePCS-PMA interface width 8, 10

Chapter 7: Custom PHY IP Core 7–5Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 7–4 shows the resulting

7–6 Chapter 7: Custom PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideWord AlignmentThe word aligne

Chapter 7: Custom PHY IP Core 7–7Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 7–6 provides more infor

7–8 Chapter 7: Custom PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide8B/10B Encoder and DecoderThe

Chapter 7: Custom PHY IP Core 7–9Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePLL Reconfiguration Table 7–1

Chapter 1: Introduction 1–3PMAMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePMAThe PMA receives and transmits differential ser

7–10 Chapter 7: Custom PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideAnalog OptionsYou specify th

Chapter 7: Custom PHY IP Core 7–11Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideXCVR_RX_BYPASS_EQ_STAGES_234

7–12 Chapter 7: Custom PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 7–12 lists the analog

Chapter 7: Custom PHY IP Core 7–13Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideXCVR_RX_EQ_BW_SELReceiver Eq

7–14 Chapter 7: Custom PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guideh For more information about

Chapter 7: Custom PHY IP Core 7–15InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterfacesThis section describes int

7–16 Chapter 7: Custom PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide <n>—The number of lanes <

Chapter 7: Custom PHY IP Core 7–17InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideThe following sections describe the

7–18 Chapter 7: Custom PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideClock InterfaceTable 7–16 describes

Chapter 7: Custom PHY IP Core 7–19InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideReset Control and Status (Optional)T

1–4 Chapter 1: IntroductionRunning a Simulation TestbenchAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideRunning a Simulation Te

7–20 Chapter 7: Custom PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideRegister InterfaceThe Avalon-MM PHY

Chapter 7: Custom PHY IP Core 7–21InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 7–20 describes the signals in

7–22 Chapter 7: Custom PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide0x042 [1:0]Wreset_control (write)Wri

Chapter 7: Custom PHY IP Core 7–23InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide0x066 [31:0] Rpma_rx_is_lockedtodata

7–24 Chapter 7: Custom PHY IP CoreSimulation Files and Example TestbenchAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideDynamic

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide8. Low Latency PHY IP CoreThe Altera Low Latency PHY IP core receives and transm

8–2 Chapter 8: Low Latency PHY IP CorePerformance and Resource UtilizationAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable

Chapter 8: Low Latency PHY IP Core 8–3Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideParameter SettingsTo con

8–4 Chapter 8: Low Latency PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 8–4 lists Standard

Chapter 8: Low Latency PHY IP Core 8–5Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAdditional OptionsThe pa

Chapter 1: Introduction 1–5Unsupported FeaturesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideThe Verilog and VHDL transceiver

8–6 Chapter 8: Low Latency PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuidePLL Reconfiguration Opti

Chapter 8: Low Latency PHY IP Core 8–7Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide1 The PLL reconfiguratio

8–8 Chapter 8: Low Latency PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideAnalog OptionsYou specif

Chapter 8: Low Latency PHY IP Core 8–9Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 8–8 lists the anal

8–10 Chapter 8: Low Latency PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideXCVR_RX_LINEAR_EQUALIZE

Chapter 8: Low Latency PHY IP Core 8–11Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideXCVR_TX_COMMON_MODE_VOL

8–12 Chapter 8: Low Latency PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guideh For more information about th

Chapter 8: Low Latency PHY IP Core 8–13InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guidef For more information about _h

8–14 Chapter 8: Low Latency PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideOptional Status InterfaceTable

Chapter 8: Low Latency PHY IP Core 8–15InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideRegister InterfaceThe Avalon-MM

1–6 Chapter 1: IntroductionUnsupported FeaturesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide

8–16 Chapter 8: Low Latency PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guidef For more information about th

Chapter 8: Low Latency PHY IP Core 8–17Simulation Files and Example TestbenchMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideDyn

8–18 Chapter 8: Low Latency PHY IP CoreSimulation Files and Example TestbenchAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide9. Deterministic Latency PHY IP CoreThe Altera Deterministic Latency PHY IP Core

9–2 Chapter 9: Deterministic Latency PHY IP CoreAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guideand status registers. This is a

Chapter 9: Deterministic Latency PHY IP Core 9–3March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAchieving Deterministic LatencyF

9–4 Chapter 9: Deterministic Latency PHY IP CoreAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideFor RE RX_latency_RE = <RX PC

Chapter 9: Deterministic Latency PHY IP Core 9–5Device Family SupportMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 9–3 s

9–6 Chapter 9: Deterministic Latency PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideParameter Sett

Chapter 9: Deterministic Latency PHY IP Core 9–7Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 9–7 list

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide2. Getting StartedThis chapter provides a general overview of the Altera IP core

9–8 Chapter 9: Deterministic Latency PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideAdditional Opt

Chapter 9: Deterministic Latency PHY IP Core 9–9Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAnalog Options

9–10 Chapter 9: Deterministic Latency PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 9–9 lis

Chapter 9: Deterministic Latency PHY IP Core 9–11Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 9–10 li

9–12 Chapter 9: Deterministic Latency PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideXCVR_RX_LINEA

Chapter 9: Deterministic Latency PHY IP Core 9–13Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideXCVR_TX_COMMO

9–14 Chapter 9: Deterministic Latency PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guideh For more informatio

Chapter 9: Deterministic Latency PHY IP Core 9–15InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide <p>—The numbe

9–16 Chapter 9: Deterministic Latency PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideAvalon-ST TX Input Da

Chapter 9: Deterministic Latency PHY IP Core 9–17InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTransceiver Serial Da

2–2 Chapter 2: Getting StartedMegaWizard Plug-In Manager FlowAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide MegaWizard™ Plug-

9–18 Chapter 9: Deterministic Latency PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideOptional Reset Contro

Chapter 9: Deterministic Latency PHY IP Core 9–19InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideFigure 9–4 illustrate

9–20 Chapter 9: Deterministic Latency PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideRegister Descriptions

Chapter 9: Deterministic Latency PHY IP Core 9–21InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideReset Controls –Manua

9–22 Chapter 9: Deterministic Latency PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideDynamic Reconfigurati

Chapter 9: Deterministic Latency PHY IP Core 9–23Channel Placement and UtilizationMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Gui

9–24 Chapter 9: Deterministic Latency PHY IP CoreSimulation Files and Example TestbenchAltera Transceiver PHY IP Core March 2012 Altera CorporationUse

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide10. Transceiver ReconfigurationControllerThe Altera Transceiver Reconfiguration

10–2 Chapter 10: Transceiver Reconfiguration ControllerAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideThis user guide describes

Chapter 10: Transceiver Reconfiguration Controller 10–3System OverviewMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideSystem Ove

Chapter 2: Getting Started 2–3MegaWizard Plug-In Manager FlowMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide2. In the Quartus I

10–4 Chapter 10: Transceiver Reconfiguration ControllerDevice Family SupportAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide1 Fo

Chapter 10: Transceiver Reconfiguration Controller 10–5Performance and Resource UtilizationMarch 2012 Altera Corporation Altera Transceiver PHY IP Cor

10–6 Chapter 10: Transceiver Reconfiguration ControllerParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 1

Chapter 10: Transceiver Reconfiguration Controller 10–7InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterfacesThis

10–8 Chapter 10: Transceiver Reconfiguration ControllerInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTransceiver Rec

Chapter 10: Transceiver Reconfiguration Controller 10–9Reconfiguration Controller Memory MapMarch 2012 Altera Corporation Altera Transceiver PHY IP Co

10–10 Chapter 10: Transceiver Reconfiguration ControllerTransceiver Calibration FunctionsAltera Transceiver PHY IP Core March 2012 Altera CorporationU

Chapter 10: Transceiver Reconfiguration Controller 10–11PMA Analog ControlsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePMA A

10–12 Chapter 10: Transceiver Reconfiguration ControllerEyeQAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guidef Refer to the DC an

Chapter 10: Transceiver Reconfiguration Controller 10–13EyeQMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideEyeQ uses a phase in

2–4 Chapter 2: Getting StartedMegaWizard Plug-In Manager FlowAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide1 The Finish button

10–14 Chapter 10: Transceiver Reconfiguration ControllerDFEAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 10–12 describes

Chapter 10: Transceiver Reconfiguration Controller 10–15DFEMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 10–14 describes

10–16 Chapter 10: Transceiver Reconfiguration ControllerAEQAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideAEQ Adaptive equaliza

Chapter 10: Transceiver Reconfiguration Controller 10–17ATX PLL CalibrationMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable

10–18 Chapter 10: Transceiver Reconfiguration ControllerPLL ReconfigurationAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable

Chapter 10: Transceiver Reconfiguration Controller 10–19PLL ReconfigurationMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideYou c

10–20 Chapter 10: Transceiver Reconfiguration ControllerPLL ReconfigurationAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable

Chapter 10: Transceiver Reconfiguration Controller 10–21Channel and PLL ReconfigurationMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUse

10–22 Chapter 10: Transceiver Reconfiguration ControllerStreamer ModuleAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide Referen

Chapter 10: Transceiver Reconfiguration Controller 10–23Streamer ModuleMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide1 All und

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide3. 10GBASE-R PHY IP CoreThe Altera 10GBASE-R PHY IP core implements the function

10–24 Chapter 10: Transceiver Reconfiguration ControllerStreamer ModuleAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 10–

Chapter 10: Transceiver Reconfiguration Controller 10–25Streamer ModuleMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideMode 1 Av

10–26 Chapter 10: Transceiver Reconfiguration ControllerStreamer ModuleAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideFor a non

Chapter 10: Transceiver Reconfiguration Controller 10–27Procedures for ReconfigurationMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser

10–28 Chapter 10: Transceiver Reconfiguration ControllerProcedures for ReconfigurationAltera Transceiver PHY IP Core March 2012 Altera CorporationUser

Chapter 10: Transceiver Reconfiguration Controller 10–29Procedures for ReconfigurationMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser

10–30 Chapter 10: Transceiver Reconfiguration ControllerProcedures for ReconfigurationAltera Transceiver PHY IP Core March 2012 Altera CorporationUser

Chapter 10: Transceiver Reconfiguration Controller 10–31Understanding Logical Channel NumberingMarch 2012 Altera Corporation Altera Transceiver PHY IP

10–32 Chapter 10: Transceiver Reconfiguration ControllerUnderstanding Logical Channel NumberingAltera Transceiver PHY IP Core March 2012 Altera Corpor

Chapter 10: Transceiver Reconfiguration Controller 10–33Understanding Logical Channel NumberingMarch 2012 Altera Corporation Altera Transceiver PHY IP

© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logosare trademar

3–2 Chapter 3: 10GBASE-R PHY IP CoreRelease InformationAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTo make most effective us

10–34 Chapter 10: Transceiver Reconfiguration ControllerUnderstanding Logical Channel NumberingAltera Transceiver PHY IP Core March 2012 Altera Corpor

Chapter 10: Transceiver Reconfiguration Controller 10–35Understanding Logical Channel NumberingMarch 2012 Altera Corporation Altera Transceiver PHY IP

10–36 Chapter 10: Transceiver Reconfiguration ControllerUnderstanding Logical Channel NumberingAltera Transceiver PHY IP Core March 2012 Altera Corpor

Chapter 10: Transceiver Reconfiguration Controller 10–37Reconfiguration Controller to PHY IP ConnectivityMarch 2012 Altera Corporation Altera Transcei

10–38 Chapter 10: Transceiver Reconfiguration ControllerMerging TX PLLs In Multiple Transceiver PHY InstancesAltera Transceiver PHY IP Core March 2012

Chapter 10: Transceiver Reconfiguration Controller 10–39Loopback ModesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideLoopback M

10–40 Chapter 10: Transceiver Reconfiguration ControllerLoopback ModesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideFigure 10–

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide11. Migrating from Stratix IV to Stratix VDevicesPreviously, Altera provided the

11–2 Chapter 11: Migrating from Stratix IV to Stratix V DevicesDynamic Reconfiguration of TransceiversAltera Transceiver PHY IP Core March 2012 Altera

Chapter 11: Migrating from Stratix IV to Stratix V Devices 11–3XAUI PHYMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide reconfig

Chapter 3: 10GBASE-R PHY IP Core 3–3Device Family SupportMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideDevice Family SupportIP

11–4 Chapter 11: Migrating from Stratix IV to Stratix V DevicesXAUI PHYAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuidePort Diff

Chapter 11: Migrating from Stratix IV to Stratix V Devices 11–5XAUI PHYMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guidetx_corecl

11–6 Chapter 11: Migrating from Stratix IV to Stratix V DevicesPHY IP Core for PCI Express PHY (PIPE)Altera Transceiver PHY IP Core March 2012 Altera

Chapter 11: Migrating from Stratix IV to Stratix V Devices 11–7PHY IP Core for PCI Express PHY (PIPE)March 2012 Altera Corporation Altera Transceiver

11–8 Chapter 11: Migrating from Stratix IV to Stratix V DevicesPHY IP Core for PCI Express PHY (PIPE)Altera Transceiver PHY IP Core March 2012 Altera

Chapter 11: Migrating from Stratix IV to Stratix V Devices 11–9PHY IP Core for PCI Express PHY (PIPE)March 2012 Altera Corporation Altera Transceiver

11–10 Chapter 11: Migrating from Stratix IV to Stratix V DevicesCustom PHYAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideCustom

Chapter 11: Migrating from Stratix IV to Stratix V Devices 11–11Custom PHYMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePort D

11–12 Chapter 11: Migrating from Stratix IV to Stratix V DevicesCustom PHYAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideHigh S

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAdditional InformationThis chapter provides additional information about the doc

3–4 Chapter 3: 10GBASE-R PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideStratix V DevicesFor Strat

Info–2 Additional InformationAdditional InformationRevision HistoryAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTransceiver R

Additional InformationAdditional Information Info–3Revision HistoryMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTransceiver R

Info–4 Additional InformationAdditional InformationRevision HistoryAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideNovember 2011

Additional InformationAdditional Information Info–5Revision HistoryMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAll ChaptersJ

Info–6 Additional InformationAdditional InformationRevision HistoryAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideMay 2011 1.2

Additional InformationAdditional Information Info–7Revision HistoryMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideCustom PHY Tr

Info–8 Additional InformationAdditional InformationRevision HistoryAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideAll ChaptersD

Additional InformationAdditional Information Info–9Revision HistoryMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideInterlaken PH

Info–10 Additional InformationAdditional InformationHow to Contact AlteraAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideHow to

Additional InformationAdditional Information Info–11Typographic ConventionsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideCouri

Chapter 3: 10GBASE-R PHY IP Core 3–5Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAnalog OptionsThe followin

Info–12 Additional InformationAdditional InformationTypographic ConventionsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide

3–6 Chapter 3: 10GBASE-R PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideStratix V DevicesYou speci

Chapter 3: 10GBASE-R PHY IP Core 3–7Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 3–7 lists the analog

3–8 Chapter 3: 10GBASE-R PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 3–8 lists the analog

Chapter 3: 10GBASE-R PHY IP Core 3–9Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideXCVR_RX_LINEAR_EQUALIZER_C

3–10 Chapter 3: 10GBASE-R PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideXCVR_TX_COMMON_MODE_VOLTA

Chapter 3: 10GBASE-R PHY IP Core 3–11InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guideh For more information about the

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideContentsChapter 1. IntroductionPCS . . . . . . . . . . . . . . . . . . . . . . .

3–12 Chapter 3: 10GBASE-R PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideSDR XGMII TX InterfaceTable 3–9 d

Chapter 3: 10GBASE-R PHY IP Core 3–13InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideSDR XGMII RX InterfaceTable 3–11

3–14 Chapter 3: 10GBASE-R PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 3–12 provides the mapping f

Chapter 3: 10GBASE-R PHY IP Core 3–15InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideThe PCS runs at 257.8125 MHz usin

3–16 Chapter 3: 10GBASE-R PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideFigure 3–5 illustrates the clock

Chapter 3: 10GBASE-R PHY IP Core 3–17InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideSerial InterfaceTable 3–15 descri

3–18 Chapter 3: 10GBASE-R PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideRegister DescriptionsTable 3–17 s

Chapter 3: 10GBASE-R PHY IP Core 3–19InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide0x044[31:0] RWreset_fine_controlY

3–20 Chapter 3: 10GBASE-R PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideDynamic ReconfigurationThis secti

Chapter 3: 10GBASE-R PHY IP Core 3–21InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 3–19 describes the signals

iv ContentsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideStratix V Devices . . . . . . . . . . . . . . . . . . . . . . . . .

3–22 Chapter 3: 10GBASE-R PHY IP CoreTimeQuest Timing ConstraintsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideAlthough you mu

Chapter 3: 10GBASE-R PHY IP Core 3–23TimeQuest Timing ConstraintsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideSynopsys Design

3–24 Chapter 3: 10GBASE-R PHY IP CoreSimulation Files and Example TestbenchAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide1 Thi

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide4. XAUI PHY IP CoreThe Altera XAUI PHY IP core implements the IEEE 802.3 Clause

4–2 Chapter 4: XAUI PHY IP CoreRelease InformationAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideRelease InformationTable 4–1 p

Chapter 4: XAUI PHY IP Core 4–3Performance and Resource UtilizationMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePerformance a

4–4 Chapter 4: XAUI PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideAnalog OptionsThe following sec

Chapter 4: XAUI PHY IP Core 4–5Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideStratix V DevicesYou specify th

4–6 Chapter 4: XAUI PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideXCVR_RX_BYPASS_EQ_STAGES_234Rec

Chapter 4: XAUI PHY IP Core 4–7Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 4–7 lists the analog para

Contents vMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideRegister Descriptions . . . . . . . . . . . . . . . . . . . . . . .

4–8 Chapter 4: XAUI PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideXCVR_RX_EQ_BW_SELReceiver Equal

Chapter 4: XAUI PHY IP Core 4–9Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guideh For more information about th

4–10 Chapter 4: XAUI PHY IP CoreConfigurationsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideConfigurationsFigure 4–2 illustrat

Chapter 4: XAUI PHY IP Core 4–11InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePortsFigure 4–3 illustrates the top-le

4–12 Chapter 4: XAUI PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideFigure 4–4 illustrates the top-level s

Chapter 4: XAUI PHY IP Core 4–13InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideFor the DDR XAUI variant, the start of

4–14 Chapter 4: XAUI PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 4–9 describes the signals in the

Chapter 4: XAUI PHY IP Core 4–15InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideClocks, Reset, and PowerdownFigure 4–8

4–16 Chapter 4: XAUI PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuidePMA Channel ControllerTable 4–13 descr

Chapter 4: XAUI PHY IP Core 4–17InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuidePMA Control and Status Interface Signa

Contents viMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideDelay Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–18 Chapter 4: XAUI PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guiderx_errdetect[7:0]OutputTransceiver 8B/

Chapter 4: XAUI PHY IP Core 4–19InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideRegistersThe Avalon-MM PHY management

4–20 Chapter 4: XAUI PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideReset Control Registers–Automatic Rese

Chapter 4: XAUI PHY IP Core 4–21InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideXAUI PCS0x082[31:4] — Reserved —[3:0]

4–22 Chapter 4: XAUI PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide0x086[31:8] — Reserved —[7:4]R, sticky

Chapter 4: XAUI PHY IP Core 4–23InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideDynamic Reconfiguration As silicon pro

4–24 Chapter 4: XAUI PHY IP CoreSimulation Files and Example TestbenchAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideDynamic Re

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide5. Interlaken PHY IP CoreInterlaken is a high speed serial communication protoco

5–2 Chapter 5: Interlaken PHY IP CoreDevice Family SupportAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide Lane-based CRC32 Di

Chapter 5: Interlaken PHY IP Core 5–3Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAdvanced OptionsTable 5–2

Contents viiMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideDirect Write Reconfiguration . . . . . . . . . . . . . . . . . . . .

5–4 Chapter 5: Interlaken PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideAnalog SettingsYou specif

Chapter 5: Interlaken PHY IP Core 5–5Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 5–5 lists the analo

5–6 Chapter 5: Interlaken PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideXCVR_RX_LINEAR_EQUALIZER_

Chapter 5: Interlaken PHY IP Core 5–7Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideXCVR_TX_COMMON_MODE_VOLTA

5–8 Chapter 5: Interlaken PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guideh For more information about the

Chapter 5: Interlaken PHY IP Core 5–9InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guidef For more information about _hw.

5–10 Chapter 5: Interlaken PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideAvalon-ST RX InterfaceTable 5–7

Chapter 5: Interlaken PHY IP Core 5–11InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guiderx_parallel_data<n>[66]Sou

5–12 Chapter 5: Interlaken PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuidePLL InterfaceTable 5–9 describes

Chapter 5: Interlaken PHY IP Core 5–13InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideRegistersThe Avalon-MM PHY manag

viii ContentsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide

5–14 Chapter 5: Interlaken PHY IP CoreInterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide0x042 [1:0]WOreset_control (writ

Chapter 5: Interlaken PHY IP Core 5–15InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTransceiver ReconfigurationAs si

5–16 Chapter 5: Interlaken PHY IP CoreTimeQuest Timing ConstraintsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 5–13 des

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide6. PHY IP Core for PCI Express (PIPE)The Altera PHY IP core for PCI Express (PI

6–2 Chapter 6: PHY IP Core for PCI Express (PIPE)Resource UtilizationAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideResource Ut

Chapter 6: PHY IP Core for PCI Express (PIPE) 6–3Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideAnalog Option

6–4 Chapter 6: PHY IP Core for PCI Express (PIPE)Parameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 6–4 lis

Chapter 6: PHY IP Core for PCI Express (PIPE) 6–5Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideTable 6–5 lis

6–6 Chapter 6: PHY IP Core for PCI Express (PIPE)Parameter SettingsAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideXCVR_RX_LINEA

Chapter 6: PHY IP Core for PCI Express (PIPE) 6–7Parameter SettingsMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideXCVR_TX_COMMO

March 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide1. IntroductionThe Altera® Transceiver PHY IP Core User Guide describes the foll

6–8 Chapter 6: PHY IP Core for PCI Express (PIPE)InterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guideh For more informatio

Chapter 6: PHY IP Core for PCI Express (PIPE) 6–9InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide1 The block diagram s

6–10 Chapter 6: PHY IP Core for PCI Express (PIPE)InterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuidePIPE InterfaceTable

Chapter 6: PHY IP Core for PCI Express (PIPE) 6–11InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guidepipe_powerdown<n&

6–12 Chapter 6: PHY IP Core for PCI Express (PIPE)InterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideFigure 6–3 illustrat

Chapter 6: PHY IP Core for PCI Express (PIPE) 6–13InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideRegistersThe Avalon-

6–14 Chapter 6: PHY IP Core for PCI Express (PIPE)InterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser GuideTable 6–11 describes

Chapter 6: PHY IP Core for PCI Express (PIPE) 6–15InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser Guide0x042 [1:0]Wreset_co

6–16 Chapter 6: PHY IP Core for PCI Express (PIPE)InterfacesAltera Transceiver PHY IP Core March 2012 Altera CorporationUser Guide0x066 [31:0] Rpma_rx

Chapter 6: PHY IP Core for PCI Express (PIPE) 6–17InterfacesMarch 2012 Altera Corporation Altera Transceiver PHY IP CoreUser GuideDynamic Reconfigurat