Altera PHY IP Core User's Guide download pdf (Page 147)

December 2010 Altera Corporation External Memory Interface Handbook Volume 3

Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide

9. Timing Diagrams

This chapter details the timing diagrams for the DDR3 SDRAM high-performance

controllers (HPC) and high-performance controllers II (HPC II).

DDR3 High-Performance Controllers

This section discusses the following timing diagrams for HPC in AFI mode:

■ “Auto-Precharge”

■ “User Refresh”

■ “Half-Rate Read for Avalon Interface”

■ “Half-Rate Write for Avalon Interface”

■ “Half Rate Write for Native Interface”

■ “Initialization Timing for HPC”

■ “Calibration Timing for HPC”

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Altera PHY IP Core User's Guide Page 147